/*==============================================================================
 Copyright (c) 2015-2018 Qualcomm Technologies, Inc.
 All Rights Reserved.
 Confidential and Proprietary - Qualcomm Technologies, Inc.
==============================================================================*/
#ifndef TITAN170_LRME_H
#define TITAN170_LRME_H

/*----------------------------------------------------------------------
        Offset and Mask
----------------------------------------------------------------------*/

#define LRME_REGS_FIRST 0x0 

#define LRME_REGS_LAST 0x9fc 

#define LRME_REGS_COUNT 0x91 

#define regLRME_LRME_CLC_HW_VERSION 0x0  /*register offset*/
#define LRME_LRME_CLC_HW_VERSION_STEP_MASK 0xffff
#define LRME_LRME_CLC_HW_VERSION_STEP_SHIFT 0x0
#define LRME_LRME_CLC_HW_VERSION_REV_MASK 0xfff0000
#define LRME_LRME_CLC_HW_VERSION_REV_SHIFT 0x10
#define LRME_LRME_CLC_HW_VERSION_GEN_MASK 0xf0000000
#define LRME_LRME_CLC_HW_VERSION_GEN_SHIFT 0x1c

#define regLRME_LRME_CLC_HW_STATUS 0x4  /*register offset*/
#define LRME_LRME_CLC_HW_STATUS_VIOLATION_MASK 0x1
#define LRME_LRME_CLC_HW_STATUS_VIOLATION_SHIFT 0x0
#define LRME_LRME_CLC_HW_STATUS_UNUSED0_MASK 0x2
#define LRME_LRME_CLC_HW_STATUS_UNUSED0_SHIFT 0x1
#define LRME_LRME_CLC_HW_STATUS_OVERWRITE_MASK 0x4
#define LRME_LRME_CLC_HW_STATUS_OVERWRITE_SHIFT 0x2
#define LRME_LRME_CLC_HW_STATUS_VIOLATION_CCIF_DS2_MASK 0x8
#define LRME_LRME_CLC_HW_STATUS_VIOLATION_CCIF_DS2_SHIFT 0x3
#define LRME_LRME_CLC_HW_STATUS_UNUSED1_MASK 0xfffffff0
#define LRME_LRME_CLC_HW_STATUS_UNUSED1_SHIFT 0x4

#define regLRME_LRME_CLC_HW_STATUS_DBG 0x8  /*register offset*/
#define LRME_LRME_CLC_HW_STATUS_DBG_TAR_HEIGHT_VIOLATION_MASK 0x1
#define LRME_LRME_CLC_HW_STATUS_DBG_TAR_HEIGHT_VIOLATION_SHIFT 0x0
#define LRME_LRME_CLC_HW_STATUS_DBG_REF_HEIGHT_VIOLATION_MASK 0x2
#define LRME_LRME_CLC_HW_STATUS_DBG_REF_HEIGHT_VIOLATION_SHIFT 0x1
#define LRME_LRME_CLC_HW_STATUS_DBG_SPARE_STATUS_MASK 0xffc
#define LRME_LRME_CLC_HW_STATUS_DBG_SPARE_STATUS_SHIFT 0x2
#define LRME_LRME_CLC_HW_STATUS_DBG_UNUSED0_MASK 0xfffff000
#define LRME_LRME_CLC_HW_STATUS_DBG_UNUSED0_SHIFT 0xc

#define regLRME_LRME_CLC_MODULE_CFG 0x60  /*register offset*/
#define LRME_LRME_CLC_MODULE_CFG_EN_MASK 0x1
#define LRME_LRME_CLC_MODULE_CFG_EN_SHIFT 0x0
#define LRME_LRME_CLC_MODULE_CFG_UNUSED0_MASK 0xfe
#define LRME_LRME_CLC_MODULE_CFG_UNUSED0_SHIFT 0x1
#define LRME_LRME_CLC_MODULE_CFG_DODOWNSCALING_MASK 0x100
#define LRME_LRME_CLC_MODULE_CFG_DODOWNSCALING_SHIFT 0x8
#define LRME_LRME_CLC_MODULE_CFG_ISNORMALIZEDSAD_MASK 0x200
#define LRME_LRME_CLC_MODULE_CFG_ISNORMALIZEDSAD_SHIFT 0x9
#define LRME_LRME_CLC_MODULE_CFG_SUBPELSEARCHENABLE_MASK 0x400
#define LRME_LRME_CLC_MODULE_CFG_SUBPELSEARCHENABLE_SHIFT 0xa
#define LRME_LRME_CLC_MODULE_CFG_SWAPINPUTS_MASK 0x800
#define LRME_LRME_CLC_MODULE_CFG_SWAPINPUTS_SHIFT 0xb
#define LRME_LRME_CLC_MODULE_CFG_DSCROPENABLE_MASK 0x1000
#define LRME_LRME_CLC_MODULE_CFG_DSCROPENABLE_SHIFT 0xc
#define LRME_LRME_CLC_MODULE_CFG_ISREFVALID_MASK 0x2000
#define LRME_LRME_CLC_MODULE_CFG_ISREFVALID_SHIFT 0xd
#define LRME_LRME_CLC_MODULE_CFG_UNUSED1_MASK 0xffffc000
#define LRME_LRME_CLC_MODULE_CFG_UNUSED1_SHIFT 0xe

#define regLRME_LRME_CLC_RANGESTEP 0x68  /*register offset*/
#define LRME_LRME_CLC_RANGESTEP_SEARCHRANGEX_MASK 0xf
#define LRME_LRME_CLC_RANGESTEP_SEARCHRANGEX_SHIFT 0x0
#define LRME_LRME_CLC_RANGESTEP_SEARCHRANGEY_MASK 0xf0
#define LRME_LRME_CLC_RANGESTEP_SEARCHRANGEY_SHIFT 0x4
#define LRME_LRME_CLC_RANGESTEP_STEPX_MASK 0xf00
#define LRME_LRME_CLC_RANGESTEP_STEPX_SHIFT 0x8
#define LRME_LRME_CLC_RANGESTEP_STEPY_MASK 0xf000
#define LRME_LRME_CLC_RANGESTEP_STEPY_SHIFT 0xc
#define LRME_LRME_CLC_RANGESTEP_UNUSED0_MASK 0xffff0000
#define LRME_LRME_CLC_RANGESTEP_UNUSED0_SHIFT 0x10

#define regLRME_LRME_CLC_OFFSET 0x6c  /*register offset*/
#define LRME_LRME_CLC_OFFSET_OFFSETX_MASK 0x1f
#define LRME_LRME_CLC_OFFSET_OFFSETX_SHIFT 0x0
#define LRME_LRME_CLC_OFFSET_OFFSETY_MASK 0x3e0
#define LRME_LRME_CLC_OFFSET_OFFSETY_SHIFT 0x5
#define LRME_LRME_CLC_OFFSET_UNUSED0_MASK 0xfffffc00
#define LRME_LRME_CLC_OFFSET_UNUSED0_SHIFT 0xa

#define regLRME_LRME_CLC_MAXALLOWEDSAD 0x70  /*register offset*/
#define LRME_LRME_CLC_MAXALLOWEDSAD_MAXALLOWEDSAD_MASK 0x7fff
#define LRME_LRME_CLC_MAXALLOWEDSAD_MAXALLOWEDSAD_SHIFT 0x0
#define LRME_LRME_CLC_MAXALLOWEDSAD_UNUSED0_MASK 0xffff8000
#define LRME_LRME_CLC_MAXALLOWEDSAD_UNUSED0_SHIFT 0xf

#define regLRME_LRME_CLC_MINALLOWEDTARMAD 0x74  /*register offset*/
#define LRME_LRME_CLC_MINALLOWEDTARMAD_MINALLOWEDTARMAD_MASK 0x3ff
#define LRME_LRME_CLC_MINALLOWEDTARMAD_MINALLOWEDTARMAD_SHIFT 0x0
#define LRME_LRME_CLC_MINALLOWEDTARMAD_UNUSED0_MASK 0xfffffc00
#define LRME_LRME_CLC_MINALLOWEDTARMAD_UNUSED0_SHIFT 0xa

#define regLRME_LRME_CLC_MEANINGFULSADDIFF 0x78  /*register offset*/
#define LRME_LRME_CLC_MEANINGFULSADDIFF_MEANINGFULSADDIFF_MASK 0x3ff
#define LRME_LRME_CLC_MEANINGFULSADDIFF_MEANINGFULSADDIFF_SHIFT 0x0
#define LRME_LRME_CLC_MEANINGFULSADDIFF_UNUSED0_MASK 0xfffffc00
#define LRME_LRME_CLC_MEANINGFULSADDIFF_UNUSED0_SHIFT 0xa

#define regLRME_LRME_CLC_MINSADDIFFDENOM 0x7c  /*register offset*/
#define LRME_LRME_CLC_MINSADDIFFDENOM_MINSADDIFFDENOM_MASK 0x3ff
#define LRME_LRME_CLC_MINSADDIFFDENOM_MINSADDIFFDENOM_SHIFT 0x0
#define LRME_LRME_CLC_MINSADDIFFDENOM_UNUSED0_MASK 0xfffffc00
#define LRME_LRME_CLC_MINSADDIFFDENOM_UNUSED0_SHIFT 0xa

#define regLRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_0 0x80  /*register offset*/
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_0_ROBUSTNESSMEASUREDISTMAP_0_MASK 0x1ff
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_0_ROBUSTNESSMEASUREDISTMAP_0_SHIFT 0x0
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_0_UNUSED0_MASK 0xfffffe00
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_0_UNUSED0_SHIFT 0x9

#define regLRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_1 0x84  /*register offset*/
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_1_ROBUSTNESSMEASUREDISTMAP_1_MASK 0x1ff
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_1_ROBUSTNESSMEASUREDISTMAP_1_SHIFT 0x0
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_1_UNUSED0_MASK 0xfffffe00
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_1_UNUSED0_SHIFT 0x9

#define regLRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_2 0x88  /*register offset*/
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_2_ROBUSTNESSMEASUREDISTMAP_2_MASK 0x1ff
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_2_ROBUSTNESSMEASUREDISTMAP_2_SHIFT 0x0
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_2_UNUSED0_MASK 0xfffffe00
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_2_UNUSED0_SHIFT 0x9

#define regLRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_3 0x8c  /*register offset*/
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_3_ROBUSTNESSMEASUREDISTMAP_3_MASK 0x1ff
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_3_ROBUSTNESSMEASUREDISTMAP_3_SHIFT 0x0
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_3_UNUSED0_MASK 0xfffffe00
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_3_UNUSED0_SHIFT 0x9

#define regLRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_4 0x90  /*register offset*/
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_4_ROBUSTNESSMEASUREDISTMAP_4_MASK 0x1ff
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_4_ROBUSTNESSMEASUREDISTMAP_4_SHIFT 0x0
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_4_UNUSED0_MASK 0xfffffe00
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_4_UNUSED0_SHIFT 0x9

#define regLRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_5 0x94  /*register offset*/
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_5_ROBUSTNESSMEASUREDISTMAP_5_MASK 0x1ff
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_5_ROBUSTNESSMEASUREDISTMAP_5_SHIFT 0x0
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_5_UNUSED0_MASK 0xfffffe00
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_5_UNUSED0_SHIFT 0x9

#define regLRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_6 0x98  /*register offset*/
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_6_ROBUSTNESSMEASUREDISTMAP_6_MASK 0x1ff
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_6_ROBUSTNESSMEASUREDISTMAP_6_SHIFT 0x0
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_6_UNUSED0_MASK 0xfffffe00
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_6_UNUSED0_SHIFT 0x9

#define regLRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_7 0x9c  /*register offset*/
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_7_ROBUSTNESSMEASUREDISTMAP_7_MASK 0x1ff
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_7_ROBUSTNESSMEASUREDISTMAP_7_SHIFT 0x0
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_7_UNUSED0_MASK 0xfffffe00
#define LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_7_UNUSED0_SHIFT 0x9

#define regLRME_LRME_CLC_DS_CROP_HORIZONTAL 0xa0  /*register offset*/
#define LRME_LRME_CLC_DS_CROP_HORIZONTAL_DSCROPHORIZSTART_MASK 0x1ff
#define LRME_LRME_CLC_DS_CROP_HORIZONTAL_DSCROPHORIZSTART_SHIFT 0x0
#define LRME_LRME_CLC_DS_CROP_HORIZONTAL_UNUSED0_MASK 0xe00
#define LRME_LRME_CLC_DS_CROP_HORIZONTAL_UNUSED0_SHIFT 0x9
#define LRME_LRME_CLC_DS_CROP_HORIZONTAL_DSCROPHORIZEND_MASK 0x3ff000
#define LRME_LRME_CLC_DS_CROP_HORIZONTAL_DSCROPHORIZEND_SHIFT 0xc
#define LRME_LRME_CLC_DS_CROP_HORIZONTAL_UNUSED1_MASK 0xffc00000
#define LRME_LRME_CLC_DS_CROP_HORIZONTAL_UNUSED1_SHIFT 0x16

#define regLRME_LRME_CLC_DS_CROP_VERTICAL 0xa4  /*register offset*/
#define LRME_LRME_CLC_DS_CROP_VERTICAL_DSCROPVERTSTART_MASK 0x3ff
#define LRME_LRME_CLC_DS_CROP_VERTICAL_DSCROPVERTSTART_SHIFT 0x0
#define LRME_LRME_CLC_DS_CROP_VERTICAL_UNUSED0_MASK 0xc00
#define LRME_LRME_CLC_DS_CROP_VERTICAL_UNUSED0_SHIFT 0xa
#define LRME_LRME_CLC_DS_CROP_VERTICAL_DSCROPVERTEND_MASK 0x3fff000
#define LRME_LRME_CLC_DS_CROP_VERTICAL_DSCROPVERTEND_SHIFT 0xc
#define LRME_LRME_CLC_DS_CROP_VERTICAL_UNUSED1_MASK 0xfc000000
#define LRME_LRME_CLC_DS_CROP_VERTICAL_UNUSED1_SHIFT 0x1a

#define regLRME_LRME_CLC_MODULEFORMAT 0xa8  /*register offset*/
#define LRME_LRME_CLC_MODULEFORMAT_REFDATAFORMAT_MASK 0x3
#define LRME_LRME_CLC_MODULEFORMAT_REFDATAFORMAT_SHIFT 0x0
#define LRME_LRME_CLC_MODULEFORMAT_UNUSED0_MASK 0xc
#define LRME_LRME_CLC_MODULEFORMAT_UNUSED0_SHIFT 0x2
#define LRME_LRME_CLC_MODULEFORMAT_TARDATAFORMAT_MASK 0x30
#define LRME_LRME_CLC_MODULEFORMAT_TARDATAFORMAT_SHIFT 0x4
#define LRME_LRME_CLC_MODULEFORMAT_UNUSED1_MASK 0xc0
#define LRME_LRME_CLC_MODULEFORMAT_UNUSED1_SHIFT 0x6
#define LRME_LRME_CLC_MODULEFORMAT_RESULTSFORMAT_MASK 0x100
#define LRME_LRME_CLC_MODULEFORMAT_RESULTSFORMAT_SHIFT 0x8
#define LRME_LRME_CLC_MODULEFORMAT_UNUSED2_MASK 0xfffffe00
#define LRME_LRME_CLC_MODULEFORMAT_UNUSED2_SHIFT 0x9

#define regLRME_LRME_CLC_TAR_PD_UNPACKER 0xac  /*register offset*/
#define LRME_LRME_CLC_TAR_PD_UNPACKER_TAR_PD_UNPACKER_PHASE_MASK 0x7
#define LRME_LRME_CLC_TAR_PD_UNPACKER_TAR_PD_UNPACKER_PHASE_SHIFT 0x0
#define LRME_LRME_CLC_TAR_PD_UNPACKER_UNUSED0_MASK 0x8
#define LRME_LRME_CLC_TAR_PD_UNPACKER_UNUSED0_SHIFT 0x3
#define LRME_LRME_CLC_TAR_PD_UNPACKER_TAR_PD_UNPACKER_LINEWIDTH_MASK 0x7ff0
#define LRME_LRME_CLC_TAR_PD_UNPACKER_TAR_PD_UNPACKER_LINEWIDTH_SHIFT 0x4
#define LRME_LRME_CLC_TAR_PD_UNPACKER_UNUSED1_MASK 0xffff8000
#define LRME_LRME_CLC_TAR_PD_UNPACKER_UNUSED1_SHIFT 0xf

#define regLRME_LRME_CLC_REF_PD_UNPACKER 0xb0  /*register offset*/
#define LRME_LRME_CLC_REF_PD_UNPACKER_REF_PD_UNPACKER_PHASE_MASK 0x7
#define LRME_LRME_CLC_REF_PD_UNPACKER_REF_PD_UNPACKER_PHASE_SHIFT 0x0
#define LRME_LRME_CLC_REF_PD_UNPACKER_UNUSED0_MASK 0x8
#define LRME_LRME_CLC_REF_PD_UNPACKER_UNUSED0_SHIFT 0x3
#define LRME_LRME_CLC_REF_PD_UNPACKER_REF_PD_UNPACKER_LINEWIDTH_MASK 0x1ff0
#define LRME_LRME_CLC_REF_PD_UNPACKER_REF_PD_UNPACKER_LINEWIDTH_SHIFT 0x4
#define LRME_LRME_CLC_REF_PD_UNPACKER_UNUSED1_MASK 0xffffe000
#define LRME_LRME_CLC_REF_PD_UNPACKER_UNUSED1_SHIFT 0xd

#define regLRME_LRME_CLC_SW_OVERRIDE 0xb4  /*register offset*/
#define LRME_LRME_CLC_SW_OVERRIDE_SW_CB_MASK 0xff
#define LRME_LRME_CLC_SW_OVERRIDE_SW_CB_SHIFT 0x0
#define LRME_LRME_CLC_SW_OVERRIDE_UNUSED0_MASK 0xffffff00
#define LRME_LRME_CLC_SW_OVERRIDE_UNUSED0_SHIFT 0x8

#define regLRME_LRME_CLC_TAR_HEIGHT 0xb8  /*register offset*/
#define LRME_LRME_CLC_TAR_HEIGHT_TAR_HEIGHT_MASK 0x3fff
#define LRME_LRME_CLC_TAR_HEIGHT_TAR_HEIGHT_SHIFT 0x0
#define LRME_LRME_CLC_TAR_HEIGHT_UNUSED0_MASK 0xffffc000
#define LRME_LRME_CLC_TAR_HEIGHT_UNUSED0_SHIFT 0xe

#define regLRME_LRME_CLC_REF_HEIGHT 0xbc  /*register offset*/
#define LRME_LRME_CLC_REF_HEIGHT_REF_HEIGHT_MASK 0x3fff
#define LRME_LRME_CLC_REF_HEIGHT_REF_HEIGHT_SHIFT 0x0
#define LRME_LRME_CLC_REF_HEIGHT_UNUSED0_MASK 0xffffc000
#define LRME_LRME_CLC_REF_HEIGHT_UNUSED0_SHIFT 0xe

#define regLRME_LRME_CLC_TEST_BUS_CTRL 0x1f8  /*register offset*/
#define LRME_LRME_CLC_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define LRME_LRME_CLC_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define LRME_LRME_CLC_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define LRME_LRME_CLC_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define LRME_LRME_CLC_TEST_BUS_CTRL_TEST_BUS_MODULE_SEL_MASK 0xf0
#define LRME_LRME_CLC_TEST_BUS_CTRL_TEST_BUS_MODULE_SEL_SHIFT 0x4
#define LRME_LRME_CLC_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0x300
#define LRME_LRME_CLC_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x8
#define LRME_LRME_CLC_TEST_BUS_CTRL_UNUSED1_MASK 0xfffffc00
#define LRME_LRME_CLC_TEST_BUS_CTRL_UNUSED1_SHIFT 0xa

#define regLRME_LRME_CLC_SPARE 0x1fc  /*register offset*/
#define LRME_LRME_CLC_SPARE_SPARE_MASK 0x1
#define LRME_LRME_CLC_SPARE_SPARE_SHIFT 0x0
#define LRME_LRME_CLC_SPARE_UNUSED0_MASK 0xfffffffe
#define LRME_LRME_CLC_SPARE_UNUSED0_SHIFT 0x1

#define regLRME_LRME_BUS_RD_HW_VERSION 0x200  /*register offset*/
#define LRME_LRME_BUS_RD_HW_VERSION_STEP_MASK 0xffff
#define LRME_LRME_BUS_RD_HW_VERSION_STEP_SHIFT 0x0
#define LRME_LRME_BUS_RD_HW_VERSION_REV_MASK 0xfff0000
#define LRME_LRME_BUS_RD_HW_VERSION_REV_SHIFT 0x10
#define LRME_LRME_BUS_RD_HW_VERSION_GEN_MASK 0xf0000000
#define LRME_LRME_BUS_RD_HW_VERSION_GEN_SHIFT 0x1c

#define regLRME_LRME_BUS_RD_HW_CAPABILITY 0x204  /*register offset*/
#define LRME_LRME_BUS_RD_HW_CAPABILITY_REG_MASK 0xff
#define LRME_LRME_BUS_RD_HW_CAPABILITY_REG_SHIFT 0x0
#define LRME_LRME_BUS_RD_HW_CAPABILITY_UBWC_MASK 0xff00
#define LRME_LRME_BUS_RD_HW_CAPABILITY_UBWC_SHIFT 0x8
#define LRME_LRME_BUS_RD_HW_CAPABILITY_LITE_MASK 0xff0000
#define LRME_LRME_BUS_RD_HW_CAPABILITY_LITE_SHIFT 0x10
#define LRME_LRME_BUS_RD_HW_CAPABILITY_FEATURE_MASK 0xff000000
#define LRME_LRME_BUS_RD_HW_CAPABILITY_FEATURE_SHIFT 0x18

#define regLRME_LRME_BUS_RD_INPUT_IF_SW_RESET 0x208  /*register offset*/
#define LRME_LRME_BUS_RD_INPUT_IF_SW_RESET_RESET_MASK 0x3
#define LRME_LRME_BUS_RD_INPUT_IF_SW_RESET_RESET_SHIFT 0x0
#define LRME_LRME_BUS_RD_INPUT_IF_SW_RESET_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_BUS_RD_INPUT_IF_SW_RESET_UNUSED0_SHIFT 0x2

#define regLRME_LRME_BUS_RD_INPUT_IF_CGC_OVERRIDE 0x20c  /*register offset*/
#define LRME_LRME_BUS_RD_INPUT_IF_CGC_OVERRIDE_CGC_OVERRIDE_MASK 0x3
#define LRME_LRME_BUS_RD_INPUT_IF_CGC_OVERRIDE_CGC_OVERRIDE_SHIFT 0x0
#define LRME_LRME_BUS_RD_INPUT_IF_CGC_OVERRIDE_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_BUS_RD_INPUT_IF_CGC_OVERRIDE_UNUSED0_SHIFT 0x2

#define regLRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK 0x210  /*register offset*/
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_INFO_RST_DONE_MASK 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_INFO_RST_DONE_SHIFT 0x0
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_INFO_REG_UPDATE_DONE_MASK 0x2
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_INFO_REG_UPDATE_DONE_SHIFT 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_INFO_RD_CLIENT_BUF_DONE_MASK 0xc
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_INFO_RD_CLIENT_BUF_DONE_SHIFT 0x2
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_UNUSED0_MASK 0xfff0
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_UNUSED0_SHIFT 0x4
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_INFO_CCIF_VIOLATION_MASK 0x30000
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_INFO_CCIF_VIOLATION_SHIFT 0x10
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_UNUSED1_MASK 0xfffc0000
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK_UNUSED1_SHIFT 0x12

#define regLRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR 0x214  /*register offset*/
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_RST_DONE_MASK 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_RST_DONE_SHIFT 0x0
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_REG_UPDATE_DONE_MASK 0x2
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_REG_UPDATE_DONE_SHIFT 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_RD_CLIENT_BUF_DONE_MASK 0xc
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_RD_CLIENT_BUF_DONE_SHIFT 0x2
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_UNUSED0_MASK 0xfff0
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_UNUSED0_SHIFT 0x4
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_CCIF_VIOLATION_MASK 0x30000
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_CCIF_VIOLATION_SHIFT 0x10
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_UNUSED1_MASK 0xfffc0000
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR_UNUSED1_SHIFT 0x12

#define regLRME_LRME_BUS_RD_INPUT_IF_IRQ_CMD 0x218  /*register offset*/
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CMD_CLEAR_MASK 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CMD_CLEAR_SHIFT 0x0
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CMD_UNUSED0_MASK 0xe
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CMD_UNUSED0_SHIFT 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CMD_SET_MASK 0x10
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CMD_SET_SHIFT 0x4
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CMD_UNUSED1_MASK 0xffffffe0
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_CMD_UNUSED1_SHIFT 0x5

#define regLRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS 0x21c  /*register offset*/
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_RST_DONE_MASK 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_RST_DONE_SHIFT 0x0
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_REG_UPDATE_DONE_MASK 0x2
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_REG_UPDATE_DONE_SHIFT 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_RD_CLIENT_BUF_DONE_MASK 0xc
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_RD_CLIENT_BUF_DONE_SHIFT 0x2
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_UNUSED0_MASK 0xfff0
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_UNUSED0_SHIFT 0x4
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_CCIF_VIOLATION_MASK 0x30000
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_CCIF_VIOLATION_SHIFT 0x10
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_UNUSED1_MASK 0xfffc0000
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS_UNUSED1_SHIFT 0x12

#define regLRME_LRME_BUS_RD_INPUT_IF_CMD 0x220  /*register offset*/
#define LRME_LRME_BUS_RD_INPUT_IF_CMD_GO_CMD_MASK 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_CMD_GO_CMD_SHIFT 0x0
#define LRME_LRME_BUS_RD_INPUT_IF_CMD_ICA_EN_MASK 0x2
#define LRME_LRME_BUS_RD_INPUT_IF_CMD_ICA_EN_SHIFT 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_CMD_UNUSED0_MASK 0x4
#define LRME_LRME_BUS_RD_INPUT_IF_CMD_UNUSED0_SHIFT 0x2
#define LRME_LRME_BUS_RD_INPUT_IF_CMD_STATIC_PRG_MASK 0x8
#define LRME_LRME_BUS_RD_INPUT_IF_CMD_STATIC_PRG_SHIFT 0x3
#define LRME_LRME_BUS_RD_INPUT_IF_CMD_UNUSED1_MASK 0xfffffff0
#define LRME_LRME_BUS_RD_INPUT_IF_CMD_UNUSED1_SHIFT 0x4

#define regLRME_LRME_BUS_RD_INPUT_IF_IRQ_SET 0x224  /*register offset*/
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_INFO_RST_DONE_MASK 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_INFO_RST_DONE_SHIFT 0x0
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_INFO_REG_UPDATE_DONE_MASK 0x2
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_INFO_REG_UPDATE_DONE_SHIFT 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_INFO_RD_CLIENT_BUF_DONE_MASK 0xc
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_INFO_RD_CLIENT_BUF_DONE_SHIFT 0x2
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_UNUSED0_MASK 0xfff0
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_UNUSED0_SHIFT 0x4
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_INFO_CCIF_VIOLATION_MASK 0x30000
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_INFO_CCIF_VIOLATION_SHIFT 0x10
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_UNUSED1_MASK 0xfffc0000
#define LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET_UNUSED1_SHIFT 0x12

#define regLRME_LRME_BUS_RD_INPUT_IF_MISR_RESET 0x22c  /*register offset*/
#define LRME_LRME_BUS_RD_INPUT_IF_MISR_RESET_RESET_MASK 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_MISR_RESET_RESET_SHIFT 0x0
#define LRME_LRME_BUS_RD_INPUT_IF_MISR_RESET_UNUSED0_MASK 0xfffffffe
#define LRME_LRME_BUS_RD_INPUT_IF_MISR_RESET_UNUSED0_SHIFT 0x1

#define regLRME_LRME_BUS_RD_INPUT_IF_SECURITY_CFG 0x230  /*register offset*/
#define LRME_LRME_BUS_RD_INPUT_IF_SECURITY_CFG_ENABLE_MASK 0x1
#define LRME_LRME_BUS_RD_INPUT_IF_SECURITY_CFG_ENABLE_SHIFT 0x0
#define LRME_LRME_BUS_RD_INPUT_IF_SECURITY_CFG_UNUSED0_MASK 0xfffffffe
#define LRME_LRME_BUS_RD_INPUT_IF_SECURITY_CFG_UNUSED0_SHIFT 0x1

#define regLRME_LRME_BUS_RD_PWR_ISO_CFG 0x234  /*register offset*/
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_PWR_ISO_ENABLE_MASK 0x1
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_PWR_ISO_ENABLE_SHIFT 0x0
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_UNUSED0_MASK 0x2
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_UNUSED0_SHIFT 0x1
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_PWR_ISO_PATGEN_SELECT_MASK 0xc
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_PWR_ISO_PATGEN_SELECT_SHIFT 0x2
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_UNUSED1_MASK 0x10
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_UNUSED1_SHIFT 0x4
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_PWR_ISO_BPP_SELECT_MASK 0x60
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_PWR_ISO_BPP_SELECT_SHIFT 0x5
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_UNUSED2_MASK 0xffffff80
#define LRME_LRME_BUS_RD_PWR_ISO_CFG_UNUSED2_SHIFT 0x7

#define regLRME_LRME_BUS_RD_PWR_ISO_SEED 0x238  /*register offset*/
#define LRME_LRME_BUS_RD_PWR_ISO_SEED_PWR_ISO_PATGEN_SEED_MASK 0xffffffff
#define LRME_LRME_BUS_RD_PWR_ISO_SEED_PWR_ISO_PATGEN_SEED_SHIFT 0x0

#define regLRME_LRME_BUS_RD_TEST_BUS_CTRL 0x248  /*register offset*/
#define LRME_LRME_BUS_RD_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define LRME_LRME_BUS_RD_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define LRME_LRME_BUS_RD_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define LRME_LRME_BUS_RD_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define LRME_LRME_BUS_RD_TEST_BUS_CTRL_TEST_BUS_CLIENT_SEL_MASK 0x1f0
#define LRME_LRME_BUS_RD_TEST_BUS_CTRL_TEST_BUS_CLIENT_SEL_SHIFT 0x4
#define LRME_LRME_BUS_RD_TEST_BUS_CTRL_TEST_BUS_INTERNAL_SEL_MASK 0xfe00
#define LRME_LRME_BUS_RD_TEST_BUS_CTRL_TEST_BUS_INTERNAL_SEL_SHIFT 0x9
#define LRME_LRME_BUS_RD_TEST_BUS_CTRL_UNUSED1_MASK 0xffff0000
#define LRME_LRME_BUS_RD_TEST_BUS_CTRL_UNUSED1_SHIFT 0x10

#define regLRME_LRME_BUS_RD_SPARE 0x24c  /*register offset*/
#define LRME_LRME_BUS_RD_SPARE_SPARE_MASK 0x1
#define LRME_LRME_BUS_RD_SPARE_SPARE_SHIFT 0x0
#define LRME_LRME_BUS_RD_SPARE_UNUSED0_MASK 0xfffffffe
#define LRME_LRME_BUS_RD_SPARE_UNUSED0_SHIFT 0x1

#define regLRME_LRME_BUS_RD_CLIENT_0_CORE_CFG 0x250  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_CORE_CFG_CLIENT_EN_MASK 0x1
#define LRME_LRME_BUS_RD_CLIENT_0_CORE_CFG_CLIENT_EN_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_0_CORE_CFG_UNUSED0_MASK 0xfffffffe
#define LRME_LRME_BUS_RD_CLIENT_0_CORE_CFG_UNUSED0_SHIFT 0x1

#define regLRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA 0x254  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_MASK 0x3
#define LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_PIXEL_PATTERN_MASK 0xfc
#define LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_PIXEL_PATTERN_SHIFT 0x2
#define LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_UNUSED0_MASK 0xffffff00
#define LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_UNUSED0_SHIFT 0x8

#define regLRME_LRME_BUS_RD_CLIENT_0_ADDR_IMAGE 0x258  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define LRME_LRME_BUS_RD_CLIENT_0_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regLRME_LRME_BUS_RD_CLIENT_0_RD_BUFFER_SIZE 0x25c  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_RD_BUFFER_SIZE_WIDTH_MASK 0xffff
#define LRME_LRME_BUS_RD_CLIENT_0_RD_BUFFER_SIZE_WIDTH_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_0_RD_BUFFER_SIZE_HEIGHT_MASK 0xffff0000
#define LRME_LRME_BUS_RD_CLIENT_0_RD_BUFFER_SIZE_HEIGHT_SHIFT 0x10

#define regLRME_LRME_BUS_RD_CLIENT_0_RD_STRIDE 0x260  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_RD_STRIDE_STRIDE_MASK 0x1fffff
#define LRME_LRME_BUS_RD_CLIENT_0_RD_STRIDE_STRIDE_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_0_RD_STRIDE_UNUSED0_MASK 0xffe00000
#define LRME_LRME_BUS_RD_CLIENT_0_RD_STRIDE_UNUSED0_SHIFT 0x15

#define regLRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0 0x264  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_MASK 0x1f
#define LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_ALIGNMENT_MASK 0x20
#define LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_ALIGNMENT_SHIFT 0x5
#define LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_UNUSED0_MASK 0xffffffc0
#define LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_UNUSED0_SHIFT 0x6

#define regLRME_LRME_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION 0x278  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION_BUFF_SIZE_MASK 0xffff
#define LRME_LRME_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION_BUFF_SIZE_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION_UNUSED0_MASK 0xffff0000
#define LRME_LRME_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION_UNUSED0_SHIFT 0x10

#define regLRME_LRME_BUS_RD_CLIENT_0_BURST_LIMIT_CFG 0x280  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_BURST_LIMIT_CFG_BURST_LENGTH_MAX_MASK 0xf
#define LRME_LRME_BUS_RD_CLIENT_0_BURST_LIMIT_CFG_BURST_LENGTH_MAX_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_0_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define LRME_LRME_BUS_RD_CLIENT_0_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regLRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_0 0x284  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_0_SAMP_MODE_MASK 0x3
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_0_SAMP_MODE_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_0_ENABLE_MASK 0x4
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_0_ENABLE_SHIFT 0x2
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_0_UNUSED0_MASK 0xfffffff8
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_0_UNUSED0_SHIFT 0x3

#define regLRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1 0x288  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_MASK 0x3
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1_UNUSED0_SHIFT 0x2

#define regLRME_LRME_BUS_RD_CLIENT_0_MISR_RD_VAL 0x28c  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_RD_VAL_MISR_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_RD_CLIENT_0_MISR_RD_VAL_MISR_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG 0x290  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regLRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_0 0x294  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_1 0x298  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_RD_CLIENT_1_CORE_CFG 0x2f0  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_CORE_CFG_CLIENT_EN_MASK 0x1
#define LRME_LRME_BUS_RD_CLIENT_1_CORE_CFG_CLIENT_EN_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_1_CORE_CFG_UNUSED0_MASK 0xfffffffe
#define LRME_LRME_BUS_RD_CLIENT_1_CORE_CFG_UNUSED0_SHIFT 0x1

#define regLRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA 0x2f4  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_STRIPE_LOCATION_MASK 0x3
#define LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_STRIPE_LOCATION_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_PIXEL_PATTERN_MASK 0xfc
#define LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_PIXEL_PATTERN_SHIFT 0x2
#define LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_UNUSED0_MASK 0xffffff00
#define LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_UNUSED0_SHIFT 0x8

#define regLRME_LRME_BUS_RD_CLIENT_1_ADDR_IMAGE 0x2f8  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define LRME_LRME_BUS_RD_CLIENT_1_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regLRME_LRME_BUS_RD_CLIENT_1_RD_BUFFER_SIZE 0x2fc  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_RD_BUFFER_SIZE_WIDTH_MASK 0xffff
#define LRME_LRME_BUS_RD_CLIENT_1_RD_BUFFER_SIZE_WIDTH_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_1_RD_BUFFER_SIZE_HEIGHT_MASK 0xffff0000
#define LRME_LRME_BUS_RD_CLIENT_1_RD_BUFFER_SIZE_HEIGHT_SHIFT 0x10

#define regLRME_LRME_BUS_RD_CLIENT_1_RD_STRIDE 0x300  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_RD_STRIDE_STRIDE_MASK 0x1fffff
#define LRME_LRME_BUS_RD_CLIENT_1_RD_STRIDE_STRIDE_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_1_RD_STRIDE_UNUSED0_MASK 0xffe00000
#define LRME_LRME_BUS_RD_CLIENT_1_RD_STRIDE_UNUSED0_SHIFT 0x15

#define regLRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0 0x304  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_MASK 0x1f
#define LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_ALIGNMENT_MASK 0x20
#define LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_ALIGNMENT_SHIFT 0x5
#define LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_UNUSED0_MASK 0xffffffc0
#define LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_UNUSED0_SHIFT 0x6

#define regLRME_LRME_BUS_RD_CLIENT_1_LATENCY_BUFF_ALLOCATION 0x318  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_LATENCY_BUFF_ALLOCATION_BUFF_SIZE_MASK 0xffff
#define LRME_LRME_BUS_RD_CLIENT_1_LATENCY_BUFF_ALLOCATION_BUFF_SIZE_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_1_LATENCY_BUFF_ALLOCATION_UNUSED0_MASK 0xffff0000
#define LRME_LRME_BUS_RD_CLIENT_1_LATENCY_BUFF_ALLOCATION_UNUSED0_SHIFT 0x10

#define regLRME_LRME_BUS_RD_CLIENT_1_BURST_LIMIT_CFG 0x320  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_BURST_LIMIT_CFG_BURST_LENGTH_MAX_MASK 0xf
#define LRME_LRME_BUS_RD_CLIENT_1_BURST_LIMIT_CFG_BURST_LENGTH_MAX_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_1_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define LRME_LRME_BUS_RD_CLIENT_1_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regLRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_0 0x324  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_0_SAMP_MODE_MASK 0x3
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_0_SAMP_MODE_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_0_ENABLE_MASK 0x4
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_0_ENABLE_SHIFT 0x2
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_0_UNUSED0_MASK 0xfffffff8
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_0_UNUSED0_SHIFT 0x3

#define regLRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1 0x328  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1_RD_WORD_SEL_MASK 0x3
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1_RD_WORD_SEL_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1_UNUSED0_SHIFT 0x2

#define regLRME_LRME_BUS_RD_CLIENT_1_MISR_RD_VAL 0x32c  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_RD_VAL_MISR_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_RD_CLIENT_1_MISR_RD_VAL_MISR_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_CFG 0x330  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regLRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_0 0x334  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_1 0x338  /*register offset*/
#define LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_WR_HW_VERSION 0x500  /*register offset*/
#define LRME_LRME_BUS_WR_HW_VERSION_STEP_MASK 0xffff
#define LRME_LRME_BUS_WR_HW_VERSION_STEP_SHIFT 0x0
#define LRME_LRME_BUS_WR_HW_VERSION_REV_MASK 0xfff0000
#define LRME_LRME_BUS_WR_HW_VERSION_REV_SHIFT 0x10
#define LRME_LRME_BUS_WR_HW_VERSION_GEN_MASK 0xf0000000
#define LRME_LRME_BUS_WR_HW_VERSION_GEN_SHIFT 0x1c

#define regLRME_LRME_BUS_WR_HW_CAPABILITY 0x504  /*register offset*/
#define LRME_LRME_BUS_WR_HW_CAPABILITY_FEATURE_MASK 0xff
#define LRME_LRME_BUS_WR_HW_CAPABILITY_FEATURE_SHIFT 0x0
#define LRME_LRME_BUS_WR_HW_CAPABILITY_LITE_MASK 0xff00
#define LRME_LRME_BUS_WR_HW_CAPABILITY_LITE_SHIFT 0x8
#define LRME_LRME_BUS_WR_HW_CAPABILITY_UBWC_MASK 0xff0000
#define LRME_LRME_BUS_WR_HW_CAPABILITY_UBWC_SHIFT 0x10
#define LRME_LRME_BUS_WR_HW_CAPABILITY_REG_MASK 0xff000000
#define LRME_LRME_BUS_WR_HW_CAPABILITY_REG_SHIFT 0x18

#define regLRME_LRME_BUS_WR_INPUT_IF_SW_RESET 0x508  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_SW_RESET_SW_RESET_MASK 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_SW_RESET_SW_RESET_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_SW_RESET_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_BUS_WR_INPUT_IF_SW_RESET_UNUSED0_SHIFT 0x2

#define regLRME_LRME_BUS_WR_INPUT_IF_CGC_OVERRIDE 0x50c  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_CGC_OVERRIDE_CGC_OVERRIGE_MASK 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_CGC_OVERRIDE_CGC_OVERRIGE_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_CGC_OVERRIDE_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_BUS_WR_INPUT_IF_CGC_OVERRIDE_UNUSED0_SHIFT 0x2

#define regLRME_LRME_BUS_WR_INPUT_IF_COMPOSITE_MASK_0 0x510  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_MASK_VEC_MASK 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_MASK_VEC_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_UNUSED0_SHIFT 0x2

#define regLRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0 0x544  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_RESET_DONE_MASK 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_RESET_DONE_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP0_BUF_DONE_MASK 0x20
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP0_BUF_DONE_SHIFT 0x5
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP1_BUF_DONE_MASK 0x40
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP1_BUF_DONE_SHIFT 0x6
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP2_BUF_DONE_MASK 0x80
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP2_BUF_DONE_SHIFT 0x7
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP3_BUF_DONE_MASK 0x100
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP3_BUF_DONE_SHIFT 0x8
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP4_BUF_DONE_MASK 0x200
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP4_BUF_DONE_SHIFT 0x9
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP5_BUF_DONE_MASK 0x400
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP5_BUF_DONE_SHIFT 0xa
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_ERROR_MASK 0x800
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_ERROR_SHIFT 0xb
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_OVERWRITE_MASK 0x1000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_OVERWRITE_SHIFT 0xc
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_OVERFLOW_ERROR_MASK 0x2000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_OVERFLOW_ERROR_SHIFT 0xd
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_VIOLATION_MASK 0x4000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_VIOLATION_SHIFT 0xe
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_UNUSED0_MASK 0xffff8000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0_UNUSED0_SHIFT 0xf

#define regLRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_1 0x548  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_1_WR_CLIENT_BUF_DONE_MASK 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED0_MASK 0xfffffc
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED0_SHIFT 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_1_EARLY_DONE_MASK 0x3000000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_1_EARLY_DONE_SHIFT 0x18
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED1_MASK 0xfc000000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED1_SHIFT 0x1a

#define regLRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0 0x550  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_RESET_DONE_MASK 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_RESET_DONE_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP0_BUF_DONE_MASK 0x20
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP0_BUF_DONE_SHIFT 0x5
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP1_BUF_DONE_MASK 0x40
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP1_BUF_DONE_SHIFT 0x6
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP2_BUF_DONE_MASK 0x80
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP2_BUF_DONE_SHIFT 0x7
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP3_BUF_DONE_MASK 0x100
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP3_BUF_DONE_SHIFT 0x8
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP4_BUF_DONE_MASK 0x200
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP4_BUF_DONE_SHIFT 0x9
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP5_BUF_DONE_MASK 0x400
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP5_BUF_DONE_SHIFT 0xa
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_ERROR_MASK 0x800
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_ERROR_SHIFT 0xb
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_OVERWRITE_MASK 0x1000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_OVERWRITE_SHIFT 0xc
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_OVERFLOW_ERROR_MASK 0x2000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_OVERFLOW_ERROR_SHIFT 0xd
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_VIOLATION_MASK 0x4000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_VIOLATION_SHIFT 0xe
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_UNUSED0_MASK 0xffff8000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0_UNUSED0_SHIFT 0xf

#define regLRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_1 0x554  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_1_WR_CLIENT_BUF_DONE_MASK 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED0_MASK 0xfffffc
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED0_SHIFT 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_1_EARLY_DONE_MASK 0x3000000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_1_EARLY_DONE_SHIFT 0x18
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED1_MASK 0xfc000000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED1_SHIFT 0x1a

#define regLRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0 0x55c  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_RESET_DONE_MASK 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_RESET_DONE_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP0_BUF_DONE_MASK 0x20
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP0_BUF_DONE_SHIFT 0x5
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP1_BUF_DONE_MASK 0x40
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP1_BUF_DONE_SHIFT 0x6
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP2_BUF_DONE_MASK 0x80
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP2_BUF_DONE_SHIFT 0x7
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP3_BUF_DONE_MASK 0x100
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP3_BUF_DONE_SHIFT 0x8
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP4_BUF_DONE_MASK 0x200
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP4_BUF_DONE_SHIFT 0x9
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP5_BUF_DONE_MASK 0x400
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP5_BUF_DONE_SHIFT 0xa
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_ERROR_MASK 0x800
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_ERROR_SHIFT 0xb
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_OVERWRITE_MASK 0x1000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_OVERWRITE_SHIFT 0xc
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_OVERFLOW_ERROR_MASK 0x2000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_OVERFLOW_ERROR_SHIFT 0xd
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_VIOLATION_MASK 0x4000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_VIOLATION_SHIFT 0xe
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_UNUSED0_MASK 0xffff8000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0_UNUSED0_SHIFT 0xf

#define regLRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_1 0x560  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_1_WR_CLIENT_BUF_DONE_MASK 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED0_MASK 0xfffffc
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED0_SHIFT 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_1_EARLY_DONE_MASK 0x3000000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_1_EARLY_DONE_SHIFT 0x18
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED1_MASK 0xfc000000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED1_SHIFT 0x1a

#define regLRME_LRME_BUS_WR_INPUT_IF_IRQ_CMD 0x568  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CMD_CLEAR_MASK 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CMD_CLEAR_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED0_MASK 0xe
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED0_SHIFT 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CMD_SET_MASK 0x10
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CMD_SET_SHIFT 0x4
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED1_MASK 0xffffffe0
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED1_SHIFT 0x5

#define regLRME_LRME_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS 0x5a8  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_FIFO_STATUS_MASK 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_FIFO_STATUS_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_UNUSED0_SHIFT 0x2

#define regLRME_LRME_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0 0x5ac  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0_CFG0_MASK 0xffffffff
#define LRME_LRME_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0_CFG0_SHIFT 0x0

#define regLRME_LRME_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1 0x5b0  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1_CFG1_MASK 0xffffffff
#define LRME_LRME_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1_CFG1_SHIFT 0x0

#define regLRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0 0x5bc  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_RESET_DONE_MASK 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_RESET_DONE_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP0_BUF_DONE_MASK 0x20
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP0_BUF_DONE_SHIFT 0x5
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP1_BUF_DONE_MASK 0x40
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP1_BUF_DONE_SHIFT 0x6
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP2_BUF_DONE_MASK 0x80
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP2_BUF_DONE_SHIFT 0x7
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP3_BUF_DONE_MASK 0x100
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP3_BUF_DONE_SHIFT 0x8
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP4_BUF_DONE_MASK 0x200
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP4_BUF_DONE_SHIFT 0x9
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP5_BUF_DONE_MASK 0x400
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP5_BUF_DONE_SHIFT 0xa
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_ERROR_MASK 0x800
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_ERROR_SHIFT 0xb
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_OVERWRITE_MASK 0x1000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_OVERWRITE_SHIFT 0xc
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_OVERFLOW_ERROR_MASK 0x2000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_OVERFLOW_ERROR_SHIFT 0xd
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_VIOLATION_MASK 0x4000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_VIOLATION_SHIFT 0xe
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_UNUSED0_MASK 0xffff8000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0_UNUSED0_SHIFT 0xf

#define regLRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_1 0x5c0  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_1_WR_CLIENT_BUF_DONE_MASK 0x3
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED0_MASK 0xfffffc
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED0_SHIFT 0x2
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_1_EARLY_DONE_MASK 0x3000000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_1_EARLY_DONE_SHIFT 0x18
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED1_MASK 0xfc000000
#define LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED1_SHIFT 0x1a

#define regLRME_LRME_BUS_WR_INPUT_IF_MISR_RESET 0x5c8  /*register offset*/
#define LRME_LRME_BUS_WR_INPUT_IF_MISR_RESET_RESET_MASK 0x1
#define LRME_LRME_BUS_WR_INPUT_IF_MISR_RESET_RESET_SHIFT 0x0
#define LRME_LRME_BUS_WR_INPUT_IF_MISR_RESET_UNUSED0_MASK 0xfffffffe
#define LRME_LRME_BUS_WR_INPUT_IF_MISR_RESET_UNUSED0_SHIFT 0x1

#define regLRME_LRME_BUS_WR_PWR_ISO_CFG 0x5cc  /*register offset*/
#define LRME_LRME_BUS_WR_PWR_ISO_CFG_PWR_ISO_ENABLE_MASK 0x1
#define LRME_LRME_BUS_WR_PWR_ISO_CFG_PWR_ISO_ENABLE_SHIFT 0x0
#define LRME_LRME_BUS_WR_PWR_ISO_CFG_UNUSED0_MASK 0xfffffffe
#define LRME_LRME_BUS_WR_PWR_ISO_CFG_UNUSED0_SHIFT 0x1

#define regLRME_LRME_BUS_WR_TEST_BUS_CTRL 0x61c  /*register offset*/
#define LRME_LRME_BUS_WR_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define LRME_LRME_BUS_WR_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define LRME_LRME_BUS_WR_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define LRME_LRME_BUS_WR_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define LRME_LRME_BUS_WR_TEST_BUS_CTRL_TEST_BUS_CLIENT_SEL_MASK 0x1f0
#define LRME_LRME_BUS_WR_TEST_BUS_CTRL_TEST_BUS_CLIENT_SEL_SHIFT 0x4
#define LRME_LRME_BUS_WR_TEST_BUS_CTRL_TEST_BUS_INTERNAL_SEL_MASK 0xfe00
#define LRME_LRME_BUS_WR_TEST_BUS_CTRL_TEST_BUS_INTERNAL_SEL_SHIFT 0x9
#define LRME_LRME_BUS_WR_TEST_BUS_CTRL_UNUSED1_MASK 0xffff0000
#define LRME_LRME_BUS_WR_TEST_BUS_CTRL_UNUSED1_SHIFT 0x10

#define regLRME_LRME_BUS_WR_SPARE 0x620  /*register offset*/
#define LRME_LRME_BUS_WR_SPARE_SPARE_MASK 0x1
#define LRME_LRME_BUS_WR_SPARE_SPARE_SHIFT 0x0
#define LRME_LRME_BUS_WR_SPARE_UNUSED0_MASK 0xfffffffe
#define LRME_LRME_BUS_WR_SPARE_UNUSED0_SHIFT 0x1

#define regLRME_LRME_BUS_WR_CLIENT_0_STATUS_0 0x700  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_STATUS_1 0x704  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_CFG 0x708  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_CFG_EN_MASK 0x1
#define LRME_LRME_BUS_WR_CLIENT_0_CFG_EN_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_0_CFG_MODE_MASK 0x2
#define LRME_LRME_BUS_WR_CLIENT_0_CFG_MODE_SHIFT 0x1
#define LRME_LRME_BUS_WR_CLIENT_0_CFG_VIRTUALFRAME_MASK 0x4
#define LRME_LRME_BUS_WR_CLIENT_0_CFG_VIRTUALFRAME_SHIFT 0x2
#define LRME_LRME_BUS_WR_CLIENT_0_CFG_UNUSED0_MASK 0xfffffff8
#define LRME_LRME_BUS_WR_CLIENT_0_CFG_UNUSED0_SHIFT 0x3

#define regLRME_LRME_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER 0x70c  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_FRAME_HEADER_CFG 0x710  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_ADDR_IMAGE 0x714  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET 0x718  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG 0x71c  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG 0x720  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define LRME_LRME_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define LRME_LRME_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regLRME_LRME_BUS_WR_CLIENT_0_PACKER_CFG 0x724  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define LRME_LRME_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define LRME_LRME_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define LRME_LRME_BUS_WR_CLIENT_0_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define LRME_LRME_BUS_WR_CLIENT_0_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regLRME_LRME_BUS_WR_CLIENT_0_WR_STRIDE 0x728  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define LRME_LRME_BUS_WR_CLIENT_0_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_0_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define LRME_LRME_BUS_WR_CLIENT_0_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regLRME_LRME_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD 0x748  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN 0x74c  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_BURST_LIMIT_CFG 0x75c  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define LRME_LRME_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define LRME_LRME_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regLRME_LRME_BUS_WR_CLIENT_0_MISR_CFG 0x760  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_CFG_EN_MASK 0x1
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_CFG_EN_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_CFG_UNUSED0_SHIFT 0x3

#define regLRME_LRME_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL 0x764  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regLRME_LRME_BUS_WR_CLIENT_0_MISR_VAL 0x768  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_VAL_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_MISR_VAL_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG 0x76c  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regLRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_0 0x770  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_1 0x774  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_STATUS_0 0x800  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_STATUS_1 0x804  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_CFG 0x808  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_CFG_EN_MASK 0x1
#define LRME_LRME_BUS_WR_CLIENT_1_CFG_EN_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_1_CFG_MODE_MASK 0x2
#define LRME_LRME_BUS_WR_CLIENT_1_CFG_MODE_SHIFT 0x1
#define LRME_LRME_BUS_WR_CLIENT_1_CFG_VIRTUALFRAME_MASK 0x4
#define LRME_LRME_BUS_WR_CLIENT_1_CFG_VIRTUALFRAME_SHIFT 0x2
#define LRME_LRME_BUS_WR_CLIENT_1_CFG_UNUSED0_MASK 0xfffffff8
#define LRME_LRME_BUS_WR_CLIENT_1_CFG_UNUSED0_SHIFT 0x3

#define regLRME_LRME_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER 0x80c  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_FRAME_HEADER_CFG 0x810  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_ADDR_IMAGE 0x814  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET 0x818  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG 0x81c  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG 0x820  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define LRME_LRME_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define LRME_LRME_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regLRME_LRME_BUS_WR_CLIENT_1_PACKER_CFG 0x824  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define LRME_LRME_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define LRME_LRME_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define LRME_LRME_BUS_WR_CLIENT_1_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define LRME_LRME_BUS_WR_CLIENT_1_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regLRME_LRME_BUS_WR_CLIENT_1_WR_STRIDE 0x828  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define LRME_LRME_BUS_WR_CLIENT_1_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_1_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define LRME_LRME_BUS_WR_CLIENT_1_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regLRME_LRME_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD 0x848  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN 0x84c  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_BURST_LIMIT_CFG 0x85c  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define LRME_LRME_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define LRME_LRME_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regLRME_LRME_BUS_WR_CLIENT_1_MISR_CFG 0x860  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_CFG_EN_MASK 0x1
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_CFG_EN_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_CFG_UNUSED0_SHIFT 0x3

#define regLRME_LRME_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL 0x864  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regLRME_LRME_BUS_WR_CLIENT_1_MISR_VAL 0x868  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_VAL_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_MISR_VAL_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG 0x86c  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regLRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_0 0x870  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regLRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_1 0x874  /*register offset*/
#define LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regLRME_LRME_TOP_HW_VERSION 0x900  /*register offset*/
#define LRME_LRME_TOP_HW_VERSION_STEP_MASK 0xffff
#define LRME_LRME_TOP_HW_VERSION_STEP_SHIFT 0x0
#define LRME_LRME_TOP_HW_VERSION_REV_MASK 0xfff0000
#define LRME_LRME_TOP_HW_VERSION_REV_SHIFT 0x10
#define LRME_LRME_TOP_HW_VERSION_GEN_MASK 0xf0000000
#define LRME_LRME_TOP_HW_VERSION_GEN_SHIFT 0x1c

#define regLRME_LRME_TOP_TITAN_VERSION 0x904  /*register offset*/
#define LRME_LRME_TOP_TITAN_VERSION_STEP_MASK 0xff
#define LRME_LRME_TOP_TITAN_VERSION_STEP_SHIFT 0x0
#define LRME_LRME_TOP_TITAN_VERSION_TIER_MASK 0xff00
#define LRME_LRME_TOP_TITAN_VERSION_TIER_SHIFT 0x8
#define LRME_LRME_TOP_TITAN_VERSION_GENERATION_MASK 0xff0000
#define LRME_LRME_TOP_TITAN_VERSION_GENERATION_SHIFT 0x10
#define LRME_LRME_TOP_TITAN_VERSION_UNUSED0_MASK 0xff000000
#define LRME_LRME_TOP_TITAN_VERSION_UNUSED0_SHIFT 0x18

#define regLRME_LRME_TOP_RST_CMD 0x908  /*register offset*/
#define LRME_LRME_TOP_RST_CMD_HW_MOD_RST_MASK 0x1
#define LRME_LRME_TOP_RST_CMD_HW_MOD_RST_SHIFT 0x0
#define LRME_LRME_TOP_RST_CMD_SW_REG_RST_MASK 0x2
#define LRME_LRME_TOP_RST_CMD_SW_REG_RST_SHIFT 0x1
#define LRME_LRME_TOP_RST_CMD_UNUSED0_MASK 0xfffffffc
#define LRME_LRME_TOP_RST_CMD_UNUSED0_SHIFT 0x2

#define regLRME_LRME_TOP_IRQ_STATUS 0x90c  /*register offset*/
#define LRME_LRME_TOP_IRQ_STATUS_RST_DONE_IRQ_MASK 0x1
#define LRME_LRME_TOP_IRQ_STATUS_RST_DONE_IRQ_SHIFT 0x0
#define LRME_LRME_TOP_IRQ_STATUS_WE_IRQ_MASK 0x2
#define LRME_LRME_TOP_IRQ_STATUS_WE_IRQ_SHIFT 0x1
#define LRME_LRME_TOP_IRQ_STATUS_FE_IRQ_MASK 0x4
#define LRME_LRME_TOP_IRQ_STATUS_FE_IRQ_SHIFT 0x2
#define LRME_LRME_TOP_IRQ_STATUS_LRME_IRQ_MASK 0x8
#define LRME_LRME_TOP_IRQ_STATUS_LRME_IRQ_SHIFT 0x3
#define LRME_LRME_TOP_IRQ_STATUS_IDLE_IRQ_MASK 0x10
#define LRME_LRME_TOP_IRQ_STATUS_IDLE_IRQ_SHIFT 0x4
#define LRME_LRME_TOP_IRQ_STATUS_UNUSED0_MASK 0xffffffe0
#define LRME_LRME_TOP_IRQ_STATUS_UNUSED0_SHIFT 0x5

#define regLRME_LRME_TOP_IRQ_MASK 0x910  /*register offset*/
#define LRME_LRME_TOP_IRQ_MASK_RST_DONE_IRQ_MASK_MASK 0x1
#define LRME_LRME_TOP_IRQ_MASK_RST_DONE_IRQ_MASK_SHIFT 0x0
#define LRME_LRME_TOP_IRQ_MASK_WE_IRQ_MASK_MASK 0x2
#define LRME_LRME_TOP_IRQ_MASK_WE_IRQ_MASK_SHIFT 0x1
#define LRME_LRME_TOP_IRQ_MASK_FE_IRQ_MASK_MASK 0x4
#define LRME_LRME_TOP_IRQ_MASK_FE_IRQ_MASK_SHIFT 0x2
#define LRME_LRME_TOP_IRQ_MASK_LRME_IRQ_MASK_MASK 0x8
#define LRME_LRME_TOP_IRQ_MASK_LRME_IRQ_MASK_SHIFT 0x3
#define LRME_LRME_TOP_IRQ_MASK_IDLE_IRQ_MASK_MASK 0x10
#define LRME_LRME_TOP_IRQ_MASK_IDLE_IRQ_MASK_SHIFT 0x4
#define LRME_LRME_TOP_IRQ_MASK_UNUSED0_MASK 0xffffffe0
#define LRME_LRME_TOP_IRQ_MASK_UNUSED0_SHIFT 0x5

#define regLRME_LRME_TOP_IRQ_CLEAR 0x914  /*register offset*/
#define LRME_LRME_TOP_IRQ_CLEAR_RST_DONE_IRQ_CLEAR_MASK 0x1
#define LRME_LRME_TOP_IRQ_CLEAR_RST_DONE_IRQ_CLEAR_SHIFT 0x0
#define LRME_LRME_TOP_IRQ_CLEAR_WE_IRQ_CLEAR_MASK 0x2
#define LRME_LRME_TOP_IRQ_CLEAR_WE_IRQ_CLEAR_SHIFT 0x1
#define LRME_LRME_TOP_IRQ_CLEAR_FE_IRQ_CLEAR_MASK 0x4
#define LRME_LRME_TOP_IRQ_CLEAR_FE_IRQ_CLEAR_SHIFT 0x2
#define LRME_LRME_TOP_IRQ_CLEAR_LRME_IRQ_CLEAR_MASK 0x8
#define LRME_LRME_TOP_IRQ_CLEAR_LRME_IRQ_CLEAR_SHIFT 0x3
#define LRME_LRME_TOP_IRQ_CLEAR_IDLE_IRQ_CLEAR_MASK 0x10
#define LRME_LRME_TOP_IRQ_CLEAR_IDLE_IRQ_CLEAR_SHIFT 0x4
#define LRME_LRME_TOP_IRQ_CLEAR_UNUSED0_MASK 0xffffffe0
#define LRME_LRME_TOP_IRQ_CLEAR_UNUSED0_SHIFT 0x5

#define regLRME_LRME_TOP_IRQ_SET 0x918  /*register offset*/
#define LRME_LRME_TOP_IRQ_SET_RST_DONE_IRQ_SET_MASK 0x1
#define LRME_LRME_TOP_IRQ_SET_RST_DONE_IRQ_SET_SHIFT 0x0
#define LRME_LRME_TOP_IRQ_SET_WE_IRQ_SET_MASK 0x2
#define LRME_LRME_TOP_IRQ_SET_WE_IRQ_SET_SHIFT 0x1
#define LRME_LRME_TOP_IRQ_SET_FE_IRQ_SET_MASK 0x4
#define LRME_LRME_TOP_IRQ_SET_FE_IRQ_SET_SHIFT 0x2
#define LRME_LRME_TOP_IRQ_SET_LRME_IRQ_SET_MASK 0x8
#define LRME_LRME_TOP_IRQ_SET_LRME_IRQ_SET_SHIFT 0x3
#define LRME_LRME_TOP_IRQ_SET_IDLE_IRQ_SET_MASK 0x10
#define LRME_LRME_TOP_IRQ_SET_IDLE_IRQ_SET_SHIFT 0x4
#define LRME_LRME_TOP_IRQ_SET_UNUSED0_MASK 0xffffffe0
#define LRME_LRME_TOP_IRQ_SET_UNUSED0_SHIFT 0x5

#define regLRME_LRME_TOP_IRQ_CMD 0x91c  /*register offset*/
#define LRME_LRME_TOP_IRQ_CMD_CLEAR_MASK 0x1
#define LRME_LRME_TOP_IRQ_CMD_CLEAR_SHIFT 0x0
#define LRME_LRME_TOP_IRQ_CMD_UNUSED0_MASK 0xe
#define LRME_LRME_TOP_IRQ_CMD_UNUSED0_SHIFT 0x1
#define LRME_LRME_TOP_IRQ_CMD_SET_MASK 0x10
#define LRME_LRME_TOP_IRQ_CMD_SET_SHIFT 0x4
#define LRME_LRME_TOP_IRQ_CMD_UNUSED1_MASK 0xffffffe0
#define LRME_LRME_TOP_IRQ_CMD_UNUSED1_SHIFT 0x5

#define regLRME_LRME_TOP_CORE_CLK_CFG 0x920  /*register offset*/
#define LRME_LRME_TOP_CORE_CLK_CFG_NOC_CLK_CGC_OVERRIDE_MASK 0x1
#define LRME_LRME_TOP_CORE_CLK_CFG_NOC_CLK_CGC_OVERRIDE_SHIFT 0x0
#define LRME_LRME_TOP_CORE_CLK_CFG_AHB_CLK_CGC_OVERRIDE_MASK 0x2
#define LRME_LRME_TOP_CORE_CLK_CFG_AHB_CLK_CGC_OVERRIDE_SHIFT 0x1
#define LRME_LRME_TOP_CORE_CLK_CFG_CORE_CLK_CGC_OVERRIDE_MASK 0x4
#define LRME_LRME_TOP_CORE_CLK_CFG_CORE_CLK_CGC_OVERRIDE_SHIFT 0x2
#define LRME_LRME_TOP_CORE_CLK_CFG_CLC_CORE_CLK_CGC_OVERRIDE_MASK 0x8
#define LRME_LRME_TOP_CORE_CLK_CFG_CLC_CORE_CLK_CGC_OVERRIDE_SHIFT 0x3
#define LRME_LRME_TOP_CORE_CLK_CFG_FE_CORE_CLK_CGC_OVERRIDE_MASK 0x10
#define LRME_LRME_TOP_CORE_CLK_CFG_FE_CORE_CLK_CGC_OVERRIDE_SHIFT 0x4
#define LRME_LRME_TOP_CORE_CLK_CFG_WE_CORE_CLK_CGC_OVERRIDE_MASK 0x20
#define LRME_LRME_TOP_CORE_CLK_CFG_WE_CORE_CLK_CGC_OVERRIDE_SHIFT 0x5
#define LRME_LRME_TOP_CORE_CLK_CFG_UNUSED0_MASK 0xffffffc0
#define LRME_LRME_TOP_CORE_CLK_CFG_UNUSED0_SHIFT 0x6

#define regLRME_LRME_TOP_VIOLATION_STATUS 0x924  /*register offset*/
#define LRME_LRME_TOP_VIOLATION_STATUS_LRME_VIOLATION_STATUS_MASK 0x1f
#define LRME_LRME_TOP_VIOLATION_STATUS_LRME_VIOLATION_STATUS_SHIFT 0x0
#define LRME_LRME_TOP_VIOLATION_STATUS_UNUSED0_MASK 0xffffffe0
#define LRME_LRME_TOP_VIOLATION_STATUS_UNUSED0_SHIFT 0x5

#define regLRME_LRME_TOP_QOS_OVERRIDE 0x928  /*register offset*/
#define LRME_LRME_TOP_QOS_OVERRIDE_WE_QOS_MASK 0xf
#define LRME_LRME_TOP_QOS_OVERRIDE_WE_QOS_SHIFT 0x0
#define LRME_LRME_TOP_QOS_OVERRIDE_FE_QOS_MASK 0xf0
#define LRME_LRME_TOP_QOS_OVERRIDE_FE_QOS_SHIFT 0x4
#define LRME_LRME_TOP_QOS_OVERRIDE_UNUSED0_MASK 0xffffff00
#define LRME_LRME_TOP_QOS_OVERRIDE_UNUSED0_SHIFT 0x8

#define regLRME_LRME_TOP_SPARE 0x9fc  /*register offset*/
#define LRME_LRME_TOP_SPARE_SPARE_MASK 0x1
#define LRME_LRME_TOP_SPARE_SPARE_SHIFT 0x0
#define LRME_LRME_TOP_SPARE_UNUSED0_MASK 0xfffffffe
#define LRME_LRME_TOP_SPARE_UNUSED0_SHIFT 0x1

/*----------------------------------------------------------------------
        Register Data Structures
----------------------------------------------------------------------*/

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _lrme_lrme_lrme_clc_hw_version;

typedef union{
    _lrme_lrme_lrme_clc_hw_version bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 1; /* 1:1 */
    unsigned  OVERWRITE : 1; /* 2:2 */
    unsigned  VIOLATION_CCIF_DS2 : 1; /* 3:3 */
    unsigned  UNUSED1 : 28; /* 31:4 */
} _lrme_lrme_lrme_clc_hw_status;

typedef union{
    _lrme_lrme_lrme_clc_hw_status bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_HW_STATUS;

typedef struct{
    unsigned  TAR_HEIGHT_VIOLATION : 1; /* 0:0 */
    unsigned  REF_HEIGHT_VIOLATION : 1; /* 1:1 */
    unsigned  SPARE_STATUS : 10; /* 11:2 */
    unsigned  UNUSED0 : 20; /* 31:12 */
} _lrme_lrme_lrme_clc_hw_status_dbg;

typedef union{
    _lrme_lrme_lrme_clc_hw_status_dbg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_HW_STATUS_DBG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  DODOWNSCALING : 1; /* 8:8 */
    unsigned  ISNORMALIZEDSAD : 1; /* 9:9 */
    unsigned  SUBPELSEARCHENABLE : 1; /* 10:10 */
    unsigned  SWAPINPUTS : 1; /* 11:11 */
    unsigned  DSCROPENABLE : 1; /* 12:12 */
    unsigned  ISREFVALID : 1; /* 13:13 */
    unsigned  UNUSED1 : 18; /* 31:14 */
} _lrme_lrme_lrme_clc_module_cfg;

typedef union{
    _lrme_lrme_lrme_clc_module_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_MODULE_CFG;

typedef struct{
    unsigned  SEARCHRANGEX : 4; /* 3:0 */
    unsigned  SEARCHRANGEY : 4; /* 7:4 */
    unsigned  STEPX : 4; /* 11:8 */
    unsigned  STEPY : 4; /* 15:12 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _lrme_lrme_lrme_clc_rangestep;

typedef union{
    _lrme_lrme_lrme_clc_rangestep bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_RANGESTEP;

typedef struct{
    unsigned  OFFSETX : 5; /* 4:0 */
    unsigned  OFFSETY : 5; /* 9:5 */
    unsigned  UNUSED0 : 22; /* 31:10 */
} _lrme_lrme_lrme_clc_offset;

typedef union{
    _lrme_lrme_lrme_clc_offset bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_OFFSET;

typedef struct{
    unsigned  MAXALLOWEDSAD : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _lrme_lrme_lrme_clc_maxallowedsad;

typedef union{
    _lrme_lrme_lrme_clc_maxallowedsad bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_MAXALLOWEDSAD;

typedef struct{
    unsigned  MINALLOWEDTARMAD : 10; /* 9:0 */
    unsigned  UNUSED0 : 22; /* 31:10 */
} _lrme_lrme_lrme_clc_minallowedtarmad;

typedef union{
    _lrme_lrme_lrme_clc_minallowedtarmad bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_MINALLOWEDTARMAD;

typedef struct{
    unsigned  MEANINGFULSADDIFF : 10; /* 9:0 */
    unsigned  UNUSED0 : 22; /* 31:10 */
} _lrme_lrme_lrme_clc_meaningfulsaddiff;

typedef union{
    _lrme_lrme_lrme_clc_meaningfulsaddiff bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_MEANINGFULSADDIFF;

typedef struct{
    unsigned  MINSADDIFFDENOM : 10; /* 9:0 */
    unsigned  UNUSED0 : 22; /* 31:10 */
} _lrme_lrme_lrme_clc_minsaddiffdenom;

typedef union{
    _lrme_lrme_lrme_clc_minsaddiffdenom bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_MINSADDIFFDENOM;

typedef struct{
    unsigned  ROBUSTNESSMEASUREDISTMAP_0 : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _lrme_lrme_lrme_clc_robustnessmeasuredistmap_0;

typedef union{
    _lrme_lrme_lrme_clc_robustnessmeasuredistmap_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_0;

typedef struct{
    unsigned  ROBUSTNESSMEASUREDISTMAP_1 : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _lrme_lrme_lrme_clc_robustnessmeasuredistmap_1;

typedef union{
    _lrme_lrme_lrme_clc_robustnessmeasuredistmap_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_1;

typedef struct{
    unsigned  ROBUSTNESSMEASUREDISTMAP_2 : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _lrme_lrme_lrme_clc_robustnessmeasuredistmap_2;

typedef union{
    _lrme_lrme_lrme_clc_robustnessmeasuredistmap_2 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_2;

typedef struct{
    unsigned  ROBUSTNESSMEASUREDISTMAP_3 : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _lrme_lrme_lrme_clc_robustnessmeasuredistmap_3;

typedef union{
    _lrme_lrme_lrme_clc_robustnessmeasuredistmap_3 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_3;

typedef struct{
    unsigned  ROBUSTNESSMEASUREDISTMAP_4 : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _lrme_lrme_lrme_clc_robustnessmeasuredistmap_4;

typedef union{
    _lrme_lrme_lrme_clc_robustnessmeasuredistmap_4 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_4;

typedef struct{
    unsigned  ROBUSTNESSMEASUREDISTMAP_5 : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _lrme_lrme_lrme_clc_robustnessmeasuredistmap_5;

typedef union{
    _lrme_lrme_lrme_clc_robustnessmeasuredistmap_5 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_5;

typedef struct{
    unsigned  ROBUSTNESSMEASUREDISTMAP_6 : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _lrme_lrme_lrme_clc_robustnessmeasuredistmap_6;

typedef union{
    _lrme_lrme_lrme_clc_robustnessmeasuredistmap_6 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_6;

typedef struct{
    unsigned  ROBUSTNESSMEASUREDISTMAP_7 : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _lrme_lrme_lrme_clc_robustnessmeasuredistmap_7;

typedef union{
    _lrme_lrme_lrme_clc_robustnessmeasuredistmap_7 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_ROBUSTNESSMEASUREDISTMAP_7;

typedef struct{
    unsigned  DSCROPHORIZSTART : 9; /* 8:0 */
    unsigned  UNUSED0 : 3; /* 11:9 */
    unsigned  DSCROPHORIZEND : 10; /* 21:12 */
    unsigned  UNUSED1 : 10; /* 31:22 */
} _lrme_lrme_lrme_clc_ds_crop_horizontal;

typedef union{
    _lrme_lrme_lrme_clc_ds_crop_horizontal bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_DS_CROP_HORIZONTAL;

typedef struct{
    unsigned  DSCROPVERTSTART : 10; /* 9:0 */
    unsigned  UNUSED0 : 2; /* 11:10 */
    unsigned  DSCROPVERTEND : 14; /* 25:12 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _lrme_lrme_lrme_clc_ds_crop_vertical;

typedef union{
    _lrme_lrme_lrme_clc_ds_crop_vertical bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_DS_CROP_VERTICAL;

typedef struct{
    unsigned  REFDATAFORMAT : 2; /* 1:0 */
    unsigned  UNUSED0 : 2; /* 3:2 */
    unsigned  TARDATAFORMAT : 2; /* 5:4 */
    unsigned  UNUSED1 : 2; /* 7:6 */
    unsigned  RESULTSFORMAT : 1; /* 8:8 */
    unsigned  UNUSED2 : 23; /* 31:9 */
} _lrme_lrme_lrme_clc_moduleformat;

typedef union{
    _lrme_lrme_lrme_clc_moduleformat bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_MODULEFORMAT;

typedef struct{
    unsigned  TAR_PD_UNPACKER_PHASE : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  TAR_PD_UNPACKER_LINEWIDTH : 11; /* 14:4 */
    unsigned  UNUSED1 : 17; /* 31:15 */
} _lrme_lrme_lrme_clc_tar_pd_unpacker;

typedef union{
    _lrme_lrme_lrme_clc_tar_pd_unpacker bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_TAR_PD_UNPACKER;

typedef struct{
    unsigned  REF_PD_UNPACKER_PHASE : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  REF_PD_UNPACKER_LINEWIDTH : 9; /* 12:4 */
    unsigned  UNUSED1 : 19; /* 31:13 */
} _lrme_lrme_lrme_clc_ref_pd_unpacker;

typedef union{
    _lrme_lrme_lrme_clc_ref_pd_unpacker bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_REF_PD_UNPACKER;

typedef struct{
    unsigned  SW_CB : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _lrme_lrme_lrme_clc_sw_override;

typedef union{
    _lrme_lrme_lrme_clc_sw_override bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_SW_OVERRIDE;

typedef struct{
    unsigned  TAR_HEIGHT : 14; /* 13:0 */
    unsigned  UNUSED0 : 18; /* 31:14 */
} _lrme_lrme_lrme_clc_tar_height;

typedef union{
    _lrme_lrme_lrme_clc_tar_height bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_TAR_HEIGHT;

typedef struct{
    unsigned  REF_HEIGHT : 14; /* 13:0 */
    unsigned  UNUSED0 : 18; /* 31:14 */
} _lrme_lrme_lrme_clc_ref_height;

typedef union{
    _lrme_lrme_lrme_clc_ref_height bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_REF_HEIGHT;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_MODULE_SEL : 4; /* 7:4 */
    unsigned  TEST_BUS_SEL : 2; /* 9:8 */
    unsigned  UNUSED1 : 22; /* 31:10 */
} _lrme_lrme_lrme_clc_test_bus_ctrl;

typedef union{
    _lrme_lrme_lrme_clc_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _lrme_lrme_lrme_clc_spare;

typedef union{
    _lrme_lrme_lrme_clc_spare bitfields,bits;
    unsigned int u32All;

} LRME_LRME_CLC_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _lrme_lrme_lrme_bus_rd_hw_version;

typedef union{
    _lrme_lrme_lrme_bus_rd_hw_version bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_HW_VERSION;

typedef struct{
    unsigned  REG : 8; /* 7:0 */
    unsigned  UBWC : 8; /* 15:8 */
    unsigned  LITE : 8; /* 23:16 */
    unsigned  FEATURE : 8; /* 31:24 */
} _lrme_lrme_lrme_bus_rd_hw_capability;

typedef union{
    _lrme_lrme_lrme_bus_rd_hw_capability bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_HW_CAPABILITY;

typedef struct{
    unsigned  RESET : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_bus_rd_input_if_sw_reset;

typedef union{
    _lrme_lrme_lrme_bus_rd_input_if_sw_reset bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_INPUT_IF_SW_RESET;

typedef struct{
    unsigned  CGC_OVERRIDE : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_bus_rd_input_if_cgc_override;

typedef union{
    _lrme_lrme_lrme_bus_rd_input_if_cgc_override bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_INPUT_IF_CGC_OVERRIDE;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_REG_UPDATE_DONE : 1; /* 1:1 */
    unsigned  INFO_RD_CLIENT_BUF_DONE : 2; /* 3:2 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  INFO_CCIF_VIOLATION : 2; /* 17:16 */
    unsigned  UNUSED1 : 14; /* 31:18 */
} _lrme_lrme_lrme_bus_rd_input_if_irq_mask;

typedef union{
    _lrme_lrme_lrme_bus_rd_input_if_irq_mask bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_INPUT_IF_IRQ_MASK;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_REG_UPDATE_DONE : 1; /* 1:1 */
    unsigned  INFO_RD_CLIENT_BUF_DONE : 2; /* 3:2 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  INFO_CCIF_VIOLATION : 2; /* 17:16 */
    unsigned  UNUSED1 : 14; /* 31:18 */
} _lrme_lrme_lrme_bus_rd_input_if_irq_clear;

typedef union{
    _lrme_lrme_lrme_bus_rd_input_if_irq_clear bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_INPUT_IF_IRQ_CLEAR;

typedef struct{
    unsigned  CLEAR : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  SET : 1; /* 4:4 */
    unsigned  UNUSED1 : 27; /* 31:5 */
} _lrme_lrme_lrme_bus_rd_input_if_irq_cmd;

typedef union{
    _lrme_lrme_lrme_bus_rd_input_if_irq_cmd bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_INPUT_IF_IRQ_CMD;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_REG_UPDATE_DONE : 1; /* 1:1 */
    unsigned  INFO_RD_CLIENT_BUF_DONE : 2; /* 3:2 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  INFO_CCIF_VIOLATION : 2; /* 17:16 */
    unsigned  UNUSED1 : 14; /* 31:18 */
} _lrme_lrme_lrme_bus_rd_input_if_irq_status;

typedef union{
    _lrme_lrme_lrme_bus_rd_input_if_irq_status bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_INPUT_IF_IRQ_STATUS;

typedef struct{
    unsigned  GO_CMD : 1; /* 0:0 */
    unsigned  ICA_EN : 1; /* 1:1 */
    unsigned  UNUSED0 : 1; /* 2:2 */
    unsigned  STATIC_PRG : 1; /* 3:3 */
    unsigned  UNUSED1 : 28; /* 31:4 */
} _lrme_lrme_lrme_bus_rd_input_if_cmd;

typedef union{
    _lrme_lrme_lrme_bus_rd_input_if_cmd bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_INPUT_IF_CMD;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_REG_UPDATE_DONE : 1; /* 1:1 */
    unsigned  INFO_RD_CLIENT_BUF_DONE : 2; /* 3:2 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  INFO_CCIF_VIOLATION : 2; /* 17:16 */
    unsigned  UNUSED1 : 14; /* 31:18 */
} _lrme_lrme_lrme_bus_rd_input_if_irq_set;

typedef union{
    _lrme_lrme_lrme_bus_rd_input_if_irq_set bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_INPUT_IF_IRQ_SET;

typedef struct{
    unsigned  RESET : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _lrme_lrme_lrme_bus_rd_input_if_misr_reset;

typedef union{
    _lrme_lrme_lrme_bus_rd_input_if_misr_reset bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_INPUT_IF_MISR_RESET;

typedef struct{
    unsigned  ENABLE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _lrme_lrme_lrme_bus_rd_input_if_security_cfg;

typedef union{
    _lrme_lrme_lrme_bus_rd_input_if_security_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_INPUT_IF_SECURITY_CFG;

typedef struct{
    unsigned  PWR_ISO_ENABLE : 1; /* 0:0 */
    unsigned  UNUSED0 : 1; /* 1:1 */
    unsigned  PWR_ISO_PATGEN_SELECT : 2; /* 3:2 */
    unsigned  UNUSED1 : 1; /* 4:4 */
    unsigned  PWR_ISO_BPP_SELECT : 2; /* 6:5 */
    unsigned  UNUSED2 : 25; /* 31:7 */
} _lrme_lrme_lrme_bus_rd_pwr_iso_cfg;

typedef union{
    _lrme_lrme_lrme_bus_rd_pwr_iso_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_PWR_ISO_CFG;

typedef struct{
    unsigned  PWR_ISO_PATGEN_SEED : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_rd_pwr_iso_seed;

typedef union{
    _lrme_lrme_lrme_bus_rd_pwr_iso_seed bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_PWR_ISO_SEED;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_CLIENT_SEL : 5; /* 8:4 */
    unsigned  TEST_BUS_INTERNAL_SEL : 7; /* 15:9 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_rd_test_bus_ctrl;

typedef union{
    _lrme_lrme_lrme_bus_rd_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _lrme_lrme_lrme_bus_rd_spare;

typedef union{
    _lrme_lrme_lrme_bus_rd_spare bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_SPARE;

typedef struct{
    unsigned  CLIENT_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _lrme_lrme_lrme_bus_rd_client_0_core_cfg;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_core_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_CORE_CFG;

typedef struct{
    unsigned  STRIPE_LOCATION : 2; /* 1:0 */
    unsigned  PIXEL_PATTERN : 6; /* 7:2 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _lrme_lrme_lrme_bus_rd_client_0_ccif_meta_data;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_ccif_meta_data bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_rd_client_0_addr_image;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_addr_image bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_ADDR_IMAGE;

typedef struct{
    unsigned  WIDTH : 16; /* 15:0 */
    unsigned  HEIGHT : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_rd_client_0_rd_buffer_size;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_rd_buffer_size bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_RD_BUFFER_SIZE;

typedef struct{
    unsigned  STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _lrme_lrme_lrme_bus_rd_client_0_rd_stride;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_rd_stride bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_RD_STRIDE;

typedef struct{
    unsigned  MODE : 5; /* 4:0 */
    unsigned  ALIGNMENT : 1; /* 5:5 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _lrme_lrme_lrme_bus_rd_client_0_unpack_cfg_0;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_unpack_cfg_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0;

typedef struct{
    unsigned  BUFF_SIZE : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_rd_client_0_latency_buff_allocation;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_latency_buff_allocation bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION;

typedef struct{
    unsigned  BURST_LENGTH_MAX : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _lrme_lrme_lrme_bus_rd_client_0_burst_limit_cfg;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_BURST_LIMIT_CFG;

typedef struct{
    unsigned  SAMP_MODE : 2; /* 1:0 */
    unsigned  ENABLE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _lrme_lrme_lrme_bus_rd_client_0_misr_cfg_0;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_misr_cfg_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_0;

typedef struct{
    unsigned  RD_WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_bus_rd_client_0_misr_cfg_1;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_misr_cfg_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1;

typedef struct{
    unsigned  MISR_VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_rd_client_0_misr_rd_val;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_misr_rd_val bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_MISR_RD_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_rd_client_0_debug_status_cfg;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_rd_client_0_debug_status_0;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_debug_status_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_rd_client_0_debug_status_1;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_0_debug_status_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_0_DEBUG_STATUS_1;

typedef struct{
    unsigned  CLIENT_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _lrme_lrme_lrme_bus_rd_client_1_core_cfg;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_core_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_CORE_CFG;

typedef struct{
    unsigned  STRIPE_LOCATION : 2; /* 1:0 */
    unsigned  PIXEL_PATTERN : 6; /* 7:2 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _lrme_lrme_lrme_bus_rd_client_1_ccif_meta_data;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_ccif_meta_data bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_rd_client_1_addr_image;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_addr_image bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_ADDR_IMAGE;

typedef struct{
    unsigned  WIDTH : 16; /* 15:0 */
    unsigned  HEIGHT : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_rd_client_1_rd_buffer_size;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_rd_buffer_size bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_RD_BUFFER_SIZE;

typedef struct{
    unsigned  STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _lrme_lrme_lrme_bus_rd_client_1_rd_stride;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_rd_stride bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_RD_STRIDE;

typedef struct{
    unsigned  MODE : 5; /* 4:0 */
    unsigned  ALIGNMENT : 1; /* 5:5 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _lrme_lrme_lrme_bus_rd_client_1_unpack_cfg_0;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_unpack_cfg_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0;

typedef struct{
    unsigned  BUFF_SIZE : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_rd_client_1_latency_buff_allocation;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_latency_buff_allocation bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_LATENCY_BUFF_ALLOCATION;

typedef struct{
    unsigned  BURST_LENGTH_MAX : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _lrme_lrme_lrme_bus_rd_client_1_burst_limit_cfg;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_BURST_LIMIT_CFG;

typedef struct{
    unsigned  SAMP_MODE : 2; /* 1:0 */
    unsigned  ENABLE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _lrme_lrme_lrme_bus_rd_client_1_misr_cfg_0;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_misr_cfg_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_0;

typedef struct{
    unsigned  RD_WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_bus_rd_client_1_misr_cfg_1;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_misr_cfg_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1;

typedef struct{
    unsigned  MISR_VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_rd_client_1_misr_rd_val;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_misr_rd_val bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_MISR_RD_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_rd_client_1_debug_status_cfg;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_rd_client_1_debug_status_0;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_debug_status_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_rd_client_1_debug_status_1;

typedef union{
    _lrme_lrme_lrme_bus_rd_client_1_debug_status_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_RD_CLIENT_1_DEBUG_STATUS_1;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _lrme_lrme_lrme_bus_wr_hw_version;

typedef union{
    _lrme_lrme_lrme_bus_wr_hw_version bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_HW_VERSION;

typedef struct{
    unsigned  FEATURE : 8; /* 7:0 */
    unsigned  LITE : 8; /* 15:8 */
    unsigned  UBWC : 8; /* 23:16 */
    unsigned  REG : 8; /* 31:24 */
} _lrme_lrme_lrme_bus_wr_hw_capability;

typedef union{
    _lrme_lrme_lrme_bus_wr_hw_capability bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_HW_CAPABILITY;

typedef struct{
    unsigned  SW_RESET : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_bus_wr_input_if_sw_reset;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_sw_reset bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_SW_RESET;

typedef struct{
    unsigned  CGC_OVERRIGE : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_bus_wr_input_if_cgc_override;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_cgc_override bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_CGC_OVERRIDE;

typedef struct{
    unsigned  MASK_VEC : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_bus_wr_input_if_composite_mask_0;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_composite_mask_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_COMPOSITE_MASK_0;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _lrme_lrme_lrme_bus_wr_input_if_irq_mask_0;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_irq_mask_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 2; /* 1:0 */
    unsigned  UNUSED0 : 22; /* 23:2 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _lrme_lrme_lrme_bus_wr_input_if_irq_mask_1;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_irq_mask_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_IRQ_MASK_1;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _lrme_lrme_lrme_bus_wr_input_if_irq_clear_0;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_irq_clear_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 2; /* 1:0 */
    unsigned  UNUSED0 : 22; /* 23:2 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _lrme_lrme_lrme_bus_wr_input_if_irq_clear_1;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_irq_clear_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_IRQ_CLEAR_1;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _lrme_lrme_lrme_bus_wr_input_if_irq_status_0;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_irq_status_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 2; /* 1:0 */
    unsigned  UNUSED0 : 22; /* 23:2 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _lrme_lrme_lrme_bus_wr_input_if_irq_status_1;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_irq_status_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_IRQ_STATUS_1;

typedef struct{
    unsigned  CLEAR : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  SET : 1; /* 4:4 */
    unsigned  UNUSED1 : 27; /* 31:5 */
} _lrme_lrme_lrme_bus_wr_input_if_irq_cmd;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_irq_cmd bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_IRQ_CMD;

typedef struct{
    unsigned  FIFO_STATUS : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_bus_wr_input_if_addr_fifo_status;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_addr_fifo_status bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS;

typedef struct{
    unsigned  CFG0 : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_input_if_frame_header_cfg0;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_frame_header_cfg0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0;

typedef struct{
    unsigned  CFG1 : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_input_if_frame_header_cfg1;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_frame_header_cfg1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _lrme_lrme_lrme_bus_wr_input_if_irq_set_0;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_irq_set_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 2; /* 1:0 */
    unsigned  UNUSED0 : 22; /* 23:2 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _lrme_lrme_lrme_bus_wr_input_if_irq_set_1;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_irq_set_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_IRQ_SET_1;

typedef struct{
    unsigned  RESET : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _lrme_lrme_lrme_bus_wr_input_if_misr_reset;

typedef union{
    _lrme_lrme_lrme_bus_wr_input_if_misr_reset bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_INPUT_IF_MISR_RESET;

typedef struct{
    unsigned  PWR_ISO_ENABLE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _lrme_lrme_lrme_bus_wr_pwr_iso_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_pwr_iso_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_PWR_ISO_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_CLIENT_SEL : 5; /* 8:4 */
    unsigned  TEST_BUS_INTERNAL_SEL : 7; /* 15:9 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_wr_test_bus_ctrl;

typedef union{
    _lrme_lrme_lrme_bus_wr_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _lrme_lrme_lrme_bus_wr_spare;

typedef union{
    _lrme_lrme_lrme_bus_wr_spare bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_SPARE;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_status_0;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_status_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_status_1;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_status_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _lrme_lrme_lrme_bus_wr_client_0_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_addr_frame_header;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_addr_frame_header bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_frame_header_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_addr_image;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_addr_image bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_addr_image_offset;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_addr_image_offset bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_buffer_width_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_wr_client_0_buffer_height_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _lrme_lrme_lrme_bus_wr_client_0_packer_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_packer_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _lrme_lrme_lrme_bus_wr_client_0_wr_stride;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_wr_stride bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_irq_subsample_cfg_period;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_irq_subsample_cfg_pattern;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _lrme_lrme_lrme_bus_wr_client_0_burst_limit_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _lrme_lrme_lrme_bus_wr_client_0_misr_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_misr_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_bus_wr_client_0_misr_rd_word_sel;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_misr_val;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_misr_val bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_wr_client_0_debug_status_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_debug_status_0;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_debug_status_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_0_debug_status_1;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_0_debug_status_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_0_DEBUG_STATUS_1;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_status_0;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_status_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_status_1;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_status_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _lrme_lrme_lrme_bus_wr_client_1_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_addr_frame_header;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_addr_frame_header bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_frame_header_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_addr_image;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_addr_image bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_addr_image_offset;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_addr_image_offset bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_buffer_width_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_wr_client_1_buffer_height_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _lrme_lrme_lrme_bus_wr_client_1_packer_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_packer_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _lrme_lrme_lrme_bus_wr_client_1_wr_stride;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_wr_stride bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_irq_subsample_cfg_period;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_irq_subsample_cfg_pattern;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _lrme_lrme_lrme_bus_wr_client_1_burst_limit_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _lrme_lrme_lrme_bus_wr_client_1_misr_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_misr_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_bus_wr_client_1_misr_rd_word_sel;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_misr_val;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_misr_val bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _lrme_lrme_lrme_bus_wr_client_1_debug_status_cfg;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_debug_status_0;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_debug_status_0 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _lrme_lrme_lrme_bus_wr_client_1_debug_status_1;

typedef union{
    _lrme_lrme_lrme_bus_wr_client_1_debug_status_1 bitfields,bits;
    unsigned int u32All;

} LRME_LRME_BUS_WR_CLIENT_1_DEBUG_STATUS_1;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _lrme_lrme_lrme_top_hw_version;

typedef union{
    _lrme_lrme_lrme_top_hw_version bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_HW_VERSION;

typedef struct{
    unsigned  STEP : 8; /* 7:0 */
    unsigned  TIER : 8; /* 15:8 */
    unsigned  GENERATION : 8; /* 23:16 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _lrme_lrme_lrme_top_titan_version;

typedef union{
    _lrme_lrme_lrme_top_titan_version bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_TITAN_VERSION;

typedef struct{
    unsigned  HW_MOD_RST : 1; /* 0:0 */
    unsigned  SW_REG_RST : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _lrme_lrme_lrme_top_rst_cmd;

typedef union{
    _lrme_lrme_lrme_top_rst_cmd bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_RST_CMD;

typedef struct{
    unsigned  RST_DONE_IRQ : 1; /* 0:0 */
    unsigned  WE_IRQ : 1; /* 1:1 */
    unsigned  FE_IRQ : 1; /* 2:2 */
    unsigned  LRME_IRQ : 1; /* 3:3 */
    unsigned  IDLE_IRQ : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _lrme_lrme_lrme_top_irq_status;

typedef union{
    _lrme_lrme_lrme_top_irq_status bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_IRQ_STATUS;

typedef struct{
    unsigned  RST_DONE_IRQ_MASK : 1; /* 0:0 */
    unsigned  WE_IRQ_MASK : 1; /* 1:1 */
    unsigned  FE_IRQ_MASK : 1; /* 2:2 */
    unsigned  LRME_IRQ_MASK : 1; /* 3:3 */
    unsigned  IDLE_IRQ_MASK : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _lrme_lrme_lrme_top_irq_mask;

typedef union{
    _lrme_lrme_lrme_top_irq_mask bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_IRQ_MASK;

typedef struct{
    unsigned  RST_DONE_IRQ_CLEAR : 1; /* 0:0 */
    unsigned  WE_IRQ_CLEAR : 1; /* 1:1 */
    unsigned  FE_IRQ_CLEAR : 1; /* 2:2 */
    unsigned  LRME_IRQ_CLEAR : 1; /* 3:3 */
    unsigned  IDLE_IRQ_CLEAR : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _lrme_lrme_lrme_top_irq_clear;

typedef union{
    _lrme_lrme_lrme_top_irq_clear bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_IRQ_CLEAR;

typedef struct{
    unsigned  RST_DONE_IRQ_SET : 1; /* 0:0 */
    unsigned  WE_IRQ_SET : 1; /* 1:1 */
    unsigned  FE_IRQ_SET : 1; /* 2:2 */
    unsigned  LRME_IRQ_SET : 1; /* 3:3 */
    unsigned  IDLE_IRQ_SET : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _lrme_lrme_lrme_top_irq_set;

typedef union{
    _lrme_lrme_lrme_top_irq_set bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_IRQ_SET;

typedef struct{
    unsigned  CLEAR : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  SET : 1; /* 4:4 */
    unsigned  UNUSED1 : 27; /* 31:5 */
} _lrme_lrme_lrme_top_irq_cmd;

typedef union{
    _lrme_lrme_lrme_top_irq_cmd bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_IRQ_CMD;

typedef struct{
    unsigned  NOC_CLK_CGC_OVERRIDE : 1; /* 0:0 */
    unsigned  AHB_CLK_CGC_OVERRIDE : 1; /* 1:1 */
    unsigned  CORE_CLK_CGC_OVERRIDE : 1; /* 2:2 */
    unsigned  CLC_CORE_CLK_CGC_OVERRIDE : 1; /* 3:3 */
    unsigned  FE_CORE_CLK_CGC_OVERRIDE : 1; /* 4:4 */
    unsigned  WE_CORE_CLK_CGC_OVERRIDE : 1; /* 5:5 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _lrme_lrme_lrme_top_core_clk_cfg;

typedef union{
    _lrme_lrme_lrme_top_core_clk_cfg bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_CORE_CLK_CFG;

typedef struct{
    unsigned  LRME_VIOLATION_STATUS : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _lrme_lrme_lrme_top_violation_status;

typedef union{
    _lrme_lrme_lrme_top_violation_status bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_VIOLATION_STATUS;

typedef struct{
    unsigned  WE_QOS : 4; /* 3:0 */
    unsigned  FE_QOS : 4; /* 7:4 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _lrme_lrme_lrme_top_qos_override;

typedef union{
    _lrme_lrme_lrme_top_qos_override bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_QOS_OVERRIDE;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _lrme_lrme_lrme_top_spare;

typedef union{
    _lrme_lrme_lrme_top_spare bitfields,bits;
    unsigned int u32All;

} LRME_LRME_TOP_SPARE;

/*----------------------------------------------------------------------
        ENUM Data Structures
----------------------------------------------------------------------*/

typedef enum{
    LRME_LRME_CLC_MODULE_CFG_ISNORMALIZEDSAD_DONT_CALCULATE_NORMALIZED_SAD  = 0x0,
    LRME_LRME_CLC_MODULE_CFG_ISNORMALIZEDSAD_CALCULATE_NORMALIZED_SAD  = 0x1
} LRME_LRME_CLC_MODULE_CFG_ISNORMALIZEDSAD_ENUM;


typedef enum{
    LRME_LRME_CLC_MODULE_CFG_SUBPELSEARCHENABLE_OPT_FLOW_DISABLED  = 0x0,
    LRME_LRME_CLC_MODULE_CFG_SUBPELSEARCHENABLE_OPT_FLOW_ENABLED  = 0x1
} LRME_LRME_CLC_MODULE_CFG_SUBPELSEARCHENABLE_ENUM;


typedef enum{
    LRME_LRME_CLC_MODULEFORMAT_REFDATAFORMAT_LINEAR_PD10  = 0x0,
    LRME_LRME_CLC_MODULEFORMAT_REFDATAFORMAT_LINEAR_PD8  = 0x1,
    LRME_LRME_CLC_MODULEFORMAT_REFDATAFORMAT_Y_ONLY_8BPS  = 0x2,
    LRME_LRME_CLC_MODULEFORMAT_REFDATAFORMAT_Y_ONLY_10BPS  = 0x3
} LRME_LRME_CLC_MODULEFORMAT_REFDATAFORMAT_ENUM;


typedef enum{
    LRME_LRME_CLC_MODULEFORMAT_TARDATAFORMAT_LINEAR_PD10  = 0x0,
    LRME_LRME_CLC_MODULEFORMAT_TARDATAFORMAT_LINEAR_PD8  = 0x1,
    LRME_LRME_CLC_MODULEFORMAT_TARDATAFORMAT_Y_ONLY_8BPS  = 0x2,
    LRME_LRME_CLC_MODULEFORMAT_TARDATAFORMAT_Y_ONLY_10BPS  = 0x3
} LRME_LRME_CLC_MODULEFORMAT_TARDATAFORMAT_ENUM;


typedef enum{
    LRME_LRME_CLC_MODULEFORMAT_RESULTSFORMAT_SHORT_FORMAT  = 0x0,
    LRME_LRME_CLC_MODULEFORMAT_RESULTSFORMAT_LONG_FORMAT  = 0x1
} LRME_LRME_CLC_MODULEFORMAT_RESULTSFORMAT_ENUM;


typedef enum{
    LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_FULL_FRAME  = 0x0,
    LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_LEFT_STRIPE  = 0x1,
    LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_RIGHT_STRIPE  = 0x2,
    LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_MIDDLE_STRIPE  = 0x3
} LRME_LRME_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_ENUM;


typedef enum{
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_BYPASS  = 0x0,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN8  = 0x1,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN16_10  = 0x2,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN16_12  = 0x3,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN16_14  = 0x4,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN32_20  = 0x5,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_ARGB16_10  = 0x6,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_ARGB16_12  = 0x7,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_ARGB16_14  = 0x8,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN32  = 0x9,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN64  = 0xa,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_TP10  = 0xb,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_MIPI8  = 0xc,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_MIPI10  = 0xd,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_MIPI12  = 0xe,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_MIPI14  = 0xf,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN16_16  = 0x10,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_BYPASS_SWAP  = 0x11,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN8_SWAP  = 0x12
} LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_ENUM;


typedef enum{
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_ALIGNMENT_LSB_ALIGNED  = 0x0,
    LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_ALIGNMENT_MSB_ALIGNED  = 0x1
} LRME_LRME_BUS_RD_CLIENT_0_UNPACK_CFG_0_ALIGNMENT_ENUM;


typedef enum{
    LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_BITS_0_31  = 0x0,
    LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_BITS_32_63  = 0x1,
    LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_BITS_64_95  = 0x2,
    LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_BITS_96_127  = 0x3
} LRME_LRME_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_ENUM;


typedef enum{
    LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_STRIPE_LOCATION_FULL_FRAME  = 0x0,
    LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_STRIPE_LOCATION_LEFT_STRIPE  = 0x1,
    LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_STRIPE_LOCATION_RIGHT_STRIPE  = 0x2,
    LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_STRIPE_LOCATION_MIDDLE_STRIPE  = 0x3
} LRME_LRME_BUS_RD_CLIENT_1_CCIF_META_DATA_STRIPE_LOCATION_ENUM;


typedef enum{
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_BYPASS  = 0x0,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_PLAIN8  = 0x1,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_PLAIN16_10  = 0x2,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_PLAIN16_12  = 0x3,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_PLAIN16_14  = 0x4,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_PLAIN32_20  = 0x5,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_ARGB16_10  = 0x6,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_ARGB16_12  = 0x7,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_ARGB16_14  = 0x8,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_PLAIN32  = 0x9,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_PLAIN64  = 0xa,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_TP10  = 0xb,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_MIPI8  = 0xc,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_MIPI10  = 0xd,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_MIPI12  = 0xe,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_MIPI14  = 0xf,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_PLAIN16_16  = 0x10,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_BYPASS_SWAP  = 0x11,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_PLAIN8_SWAP  = 0x12
} LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_MODE_ENUM;


typedef enum{
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_ALIGNMENT_LSB_ALIGNED  = 0x0,
    LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_ALIGNMENT_MSB_ALIGNED  = 0x1
} LRME_LRME_BUS_RD_CLIENT_1_UNPACK_CFG_0_ALIGNMENT_ENUM;


typedef enum{
    LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1_RD_WORD_SEL_BITS_0_31  = 0x0,
    LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1_RD_WORD_SEL_BITS_32_63  = 0x1,
    LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1_RD_WORD_SEL_BITS_64_95  = 0x2,
    LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1_RD_WORD_SEL_BITS_96_127  = 0x3
} LRME_LRME_BUS_RD_CLIENT_1_MISR_CFG_1_RD_WORD_SEL_ENUM;

#endif // TITAN170_LRME_H
